2000 Nov 09
11
Philips Semiconductors
Product specification
Double multiprotocol IC card interface
TDA8007B
G
ENERAL REGISTERS
The Card Select Register (see Table 1) is used for
selecting the card on which the UART will act, and also to
reset the ISO UART.
If SC1 = 1, then card 1 is selected; if SC2 = 1, then card 2
is selected, if SC3 = 1, then card 3 is selected. These bits
must be set one at a time. After reset, card 1 is selected by
default. The bit Reset ISO UART (RIU) must be set to
logic 1 by software before any action on the UART can
take place. When reset, this bit resets all UART registers
to their initial value.
It should be noted that access to card 3 is only possible
once either card 1 or 2 has been activated.
The Hardware Status Register (see Table 2) gives the
status of the chip after a hardware problem has been
detected.
Presence Latch 1 (PRL1) and Presence Latch 2 (PRL2)
are HIGH when a change has occurred on PR1 and PR2.
SupervisorLatch(SUPL)isHIGHwhenthesupervisorhas
been activated.
Protection 1 (PRTL1) and Protection 2 (PRTL2) are HIGH
when a default has been detected on card readers 1
and 2. (PRTL is the OR function of protection on V
CC
and
RST).
PTL is set if overheating has occurred.
INTAUXL is HIGH if the level on the INTAUX input has
been changed.
When PRTL2, PRTL1, PRL2 or PRL1 or PTL is HIGH,
then INT is LOW. The bits having caused the interrupt are
cleared when the HSR has been read-out. The same
occurs with bit INTAUXL if not disabled.
At power-on, or after a supply voltage dropout, SUPL is set
and INT is LOW. INT will return HIGH at the end of the
alarm pulse on pin RSTOUT. SUPL will be reset only after
a status register read-out outside the ALARM pulse
(see Fig.7).
In case of emergency deactivation (by PRTL1, PRTL2,
SUPL, PRL2, PRL1 or PTL), the START bit is
automatically reset by hardware.
The three registers TOR1, TOR2 and TOR3 form a
programmable 24-bit ETU counter, or two independant
counters (one 16-bit and one 8-bit).
The value to load in TOR1, 2 and 3 is the number of ETUs
to count.
The TOC register is used for setting different
configurations of the time-out counter as given in Table 7
(all other configurations are undefined).
Table 1
Card select register (write and read); address: 0
(all significant bits are cleared after reset, except for SC1 which is set)
Table 2
Hardware status register (read only); address: F
(all significant bits are cleared after reset, except for SUPL which is set within the RSTOUT pulse)
Table 3
Time-out register 1 (write only); address: 9 (all bits are cleared after reset)
Table 4
Time-out register 2 (write only); address: A (all bits are cleared after reset)
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
not used
not used
not used
not used
RIU
SC3
SC2
SC1
HS7
HS6
HS5
HS4
HS3
HS2
HS1
HS0
not used
PRTL2
PRTL1
SUPL
PRL2
PRL1
INTAUXL
PTL
TO17
TO16
TO15
TO14
TO13
TO12
TO11
TO10
TOL7
TOL6
TOL5
TOL4
TOL3
TOL2
TOL1
TOL0
TO27
TO26
TO25
TO24
TO23
TO22
TO21
TO20
TOL15
TOL14
TOL13
TOL12
TOL11
TOL10
TOL9
TOL8