參數(shù)資料
型號(hào): TDA8007B
廠商: NXP Semiconductors N.V.
英文描述: IC LOGIC 1G02 SINGLE 2-INPUT POSITIVE-NOR GATE -40+85C SOT-23-5 3000/REEL
中文描述: 雙IC卡接口的多協(xié)議
文件頁(yè)數(shù): 16/36頁(yè)
文件大?。?/td> 159K
代理商: TDA8007B
2000 Nov 09
16
Philips Semiconductors
Product specification
Double multiprotocol IC card interface
TDA8007B
C
ARD REGISTERS
When cards 1 2 or 3 are selected, then the following registers may be used for programming some specific parameters.
The Programmable Divider Register (see Table 13) is used for counting the cards clock cycles forming the ETU. It is an
auto-reload 8-bit counter decounting from the programmed value down to 0.
Table 13
Programmable Divider Register (PDR1, 2 and 3) (read and write); address: 2 (all bits are cleared after reset)
The UART Configuration Register 2 bits are given in Table 14. If bit PSC is set to logic 1, then the prescaler value is 32.
If bit PSC is set to logic 0, then the prescaler value is 31. One ETU will last a number of card clock cycles equal to
prescaler x PDR. All baud rates specified in ISO 7816 norm are achievable with this configuration.
Table 14
UART configuration register 2 (UCR21, 22 and 23) (read and write); address: 3
(all relevant bits are cleared after reset)
Table 15
Baud rates with a 3.58 MHz card clock frequency (31;12 means prescaler set to 31 and PDR set to 12)
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
UC27
UC26
UC25
UC24
UC23
UC22
UC21
UC20
not used
DISTBE/RBF
DISAUX
PDWN
SAN
AUTOCONV
CKU
PSC
D
F
0
1
2
3
4
5
6
9
10
11
12
13
1
31;12
9600
31;6
19200
31;3
38400
31;12
9600
31;6
19200
31;3
38400
31;18
6400
31;9
12800
31;24
4800
31;12
9600
31;6
19200
31;3
38400
31;36
3200
31;18
6400
31;9
12800
31;48
2400
31;24
4800
31;12
9600
31;6
19200
31;3
38400
31;60
1920
31;30
3840
31;15
7680
32;16
32;24
32;32
32;48
32;64
2
32;8
32;12
32;16
32;24
32;32
3
32;4
32;6
32;8
32;12
32;16
4
32;2
32;3
32;4
32;6
32;8
5
32;1
32;2
32;3
32;4
6
8
32;1
32;2
31;1
115200
31;1
115200
31;2
57600
31;3
38400
31;4
28800
31;5
23040
31;3
38400
32;2
32;4
9
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