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參數(shù)資料
| 型號： | THS1031IPWLE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 10-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 296K |
| 代理商： | THS1031IPWLE |
THS1031
COMPLETE SOLUTION 2.7 V ~ 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242 – NOVEMBER 1999
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clamp operation (continued)
D Clamp and Droop Analysis
16–Bit DAC
SW2
SW1
AIN
CLAMP
CLAMPIN
+
–
C1
R1
S/H
Control
Register
Figure 14. Clamp Operation
D Clamp Acquisition Time: Figure 14 shows the basic operation of the clamp circuit in which the ac input
signal is passed through an RC coupler.
The acquisition time when the switch is closed will equal a: T(acq) = Ci.Ri ln(Vc/Ve)(Eq.1)
In case of composite video, typical input Ri = 20
. In a video clamping application, the droop is a critical
parameter and thus the input capacitor should be sized to allow sufficient acquisition time of clamp voltage at
AIN within the CLAMP interval, but also to minimize droop between clamping intervals. Typically, Ci = 1F
By applying equation 1 above, the following examples apply to an NTSC composite video signal:
D The acquisition time needed to clamp 1-V input level to black level (0.340 Vdc ) is about 130 s.
D The acquisition time needed to clamp 2-V input level to the white level (1 Vdc) is about 140 s.
D The acquisition time needed to clamp 3-V input level to the sync level (0.288 Vdc) is about 160 s.
droop
The voltage droop is the voltage change across the input capacitor Ci by the bias current as follows:
dV
+ I
bias Ci (t)
where t = elapsed time between clamping intervals
The bias current depends on the sampling rate. For a sampling rate of 30 MSPS and a typical input capacitance
of 1 pF, the input resistance is
Rs = 1/(Cs.Fs) = 1/(1 pFx30 MHz) = 33 k
For 1-V input range and clamping period = 64
s, the max bias current will equal Ibias = 0.5 V/33 k = 15 A:
dV = (15
A/1 F)(64 s) = 0.96 mV
For 1-V input range and clamping period = 64
s, the max bias current will equal Ibias = 0.5 V/33 k = 15 A:
dV = (15
A/1 F)(64 s) = 0.96 mV
For 2-V input range and clamping period = 64
s, the max bias current will equal Ibias = 1.0 V/33 k = 30 A
dV = (30
A/1 F)(64 s) = 1.9 mV
PRODUCT
PREVIEW
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| THS1031IPWR | 功能描述:模數(shù)轉換器 - ADC 10-Bit 30 MSPS 1-Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1031IPWRG4 | 功能描述:模數(shù)轉換器 - ADC 10-Bit 30 MSPS 1-Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1031SOIC | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER |
| THS1031TSSOP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER |
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