參數(shù)資料
型號: THS1031IPWLE
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 10-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: PLASTIC, TSSOP-28
文件頁數(shù): 11/22頁
文件大?。?/td> 296K
代理商: THS1031IPWLE
THS1031
COMPLETE SOLUTION 2.7 V ~ 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242 – NOVEMBER 1999
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clamp operation (continued)
requirements
For a single direct source of NTSC video,
D The initial clamp acquisition time needs to be between 130 s and 160 s to set the input dc level within
1 mV accuracy.
D The clamp pulse at CLAMP is recommended to be 2 s (typ)
D The droop voltage needs to be compensated within one clamping period of 64 s for 1 V and 2 V. Input
ranges are 1 mV and 1.9 mV respectively which are less than 1 LSB.
power management
Upon power up, the THS1031 is put in the default mode. In the default mode, the PGA (PGA bypass) and the
clamp DAC are powered down which adds to the device’s flexibility. The users need not incur the penalty of
having to provide power for a certain section if it is not necessary to their design.
When bit 3 of PGA/control register is set to 1, the entire device is powered down. The ADC will wake-up in 400 ns
(typ) after the bit 3 is reset.
PRODUCT
PREVIEW
相關(guān)PDF資料
PDF描述
THS1031CPWLE 10-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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THS1040IPW 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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