參數(shù)資料
型號: THS5641AIPWR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁數(shù): 28/31頁
文件大?。?/td> 915K
代理商: THS5641AIPWR
THS5641A
8BIT, 100 MSPS, CommsDAC
DIGITALTOANALOG CONVERTER
SLAS277A MARCH 2000 REVISED SEPTEMBER 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, IOUTFS = 20 mA, single-ended output IOUT1, 50 doubly terminated load (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC linearity (to Nyquist)
fCLK = 5 MSPS, fOUT = 1 MHz, TA = 25°C
68
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25°C
69
fCLK = 25 MSPS, fOUT = 5 MHz, TA = 25°C
68
fCLK = 25 MSPS, fOUT = 10 MHz, TA = 25°C
56
fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25°C
67
fCLK = 50 MSPS, fOUT = 5 MHz, TA = 25°C
67
SFDR
Spurious free dynamic range
fCLK = 50 MSPS, fOUT = 20 MHz, TA = 25°C
53
dBc
SFDR
Spurious free dynamic range
fCLK = 70 MSPS, fOUT = 5 MHz, TA = 25°C
65
dBc
fCLK = 70 MSPS, fOUT = 10 MHz, TA = 25°C
63
fCLK = 70 MSPS, fOUT = 20 MHz, TA = 25°C
48
fCLK = 100 MSPS, fOUT = 10 MHz, TA = 25°C
55
fCLK = 100 MSPS, fOUT = 22 MHz, TA = 25°C
55
fCLK = 100 MSPS, fOUT = 40 MHz, TA = 25°C
48
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Interface
VIH
High-level input voltage
DVDD = 5 V
3.5
5
V
VIH
High-level input voltage
DVDD = 3.3 V
2.1
3.3
V
VIL
Low-level input voltage
DVDD = 5 V
0
1.3
V
VIL
Low-level input voltage
DVDD = 3.3 V
0
0.9
V
IIH
High-level input current
MODE and SLEEP
DVDD = 3 V to 5.5 V
15
A
IIH
High-level input current
All other digital pins
DVDD = 3 V to 5.5 V
10
A
IIL
Low-level input current
MODE and SLEEP
DVDD = 3 V to 5.5 V
15
A
IIL
Low-level input current
All other digital pins
DVDD = 3 V to 5.5 V
10
A
CI
Input capacitance
1
5
pF
Timing
tsu(D)
Input setup time
1
ns
th(D)
Input hold time
1
ns
tw(LPH)
Input latch pulse high time
4
ns
td(D)
Digital delay time
1
clk
Specifications subject to change
相關(guān)PDF資料
PDF描述
THS5641AIDWRG4 PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
THS5641AIDWG4 PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
THS5641AIPWRG4 PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
THS5641AIDWR PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
THS5641IDWR PARALLEL, 8 BITS INPUT LOADING, 0.035 us SETTLING TIME, 8-BIT DAC, PDSO28
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