- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385925 > THS8133ATQFP (Texas Instruments, Inc.) TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION PDF資料下載
參數(shù)資料
| 型號： | THS8133ATQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION |
| 中文描述： | 三路10位，80 MSPS的視頻D /與Tri轉(zhuǎn)爐電平同步發(fā)電 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大?。?/td> | 339K |
| 代理商： | THS8133ATQFP |
THS8133, THS8133A, THS8133B
TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AVAILABLE OPTIONS
TA
PACKAGE
TQFP-48 PowerPAD
THS8133CPHP
THS8133ACPHP
THS8133BCPHP
0 C to 70 C
In the THS8133CPHP, the KIMBAL maximum specification is
assured over full temperature range and the KIMBAL(SYNC)
maximum specification is assured at 25
°
C. The position of
the blanking level is as shown in Table 1.
In the THS8133ACPHP and the THS8133BCPHP, both the
KIMBAL maximum speciffication and the KIMBAL(SYNC)
maximum specification are assured over the full temperature
range. The position of the blanking level is as shown in Table
1.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
ABPb
PIN
45
O
Analog red, green and blue respectively Pr, Y and Pb current outputs, capable of directly driving a doubly
terminated 75-
coaxial cable.
AGY
41
O
ARPr
43
O
AVDD
AVSS
BLANK
40,44
I
Analog power supply (5 V
±
10%). All AVDD terminals must be connected.
Analog ground
42,46
I
23
I
Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY and
ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes
precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) will result in sync generation.
BPb0–BPb9
10–1
I
Blue or Pb pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
different operating modes.
CLK
26
I
Clock input. A rising edge on CLK latches RPr0-9, GY0-9, BPb0-9, BLANK, SYNC, and SYNC_T. The M2 input is
latched by a rising edge on CLK also, but only when additional conditions are satisfied, as explained in its
terminal description.
Compensation terminal. A 0.1
μ
F capacitor must be connected between COMP and AVDD.
Digital power supply (3-V to 5-V range)
COMP
39
O
DVDD
DVSS
FSADJ
12
I
11
I
Digital ground
38
I
Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value of
a resistor RFS connected between this terminal and AVSS. The nominal value of RFS is 430
, corresponding to
26.67 mA full-scale current. The relationship between RFS and the full-scale current level for each operation
mode is explained in the functional description.
GY0–GY9
36–27
I
Green or Y pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
different operating modes.
M1
47
I
Operation mode control 1. M1 is directly interpreted by the device (it is not latched by CLK). M1 configures device
according to Table 1.
M2
48
I
Operation mode control 2. The second rising edge on CLK after a transition on SYNC latches M2. The
interpretation is dependent on the polarity of the last SYNC transition:
SYNC L to H: latched as M2_INT
SYNC H to L: latched as INS3_INT
Together with M1, M2_INT configures the device as shown in Table 1. When INS3_INT is high, the sync output is
inserted on all DAC outputs; a low will insert it only on the AGY output. See also Figure 2 and Table 2. The value of
M2 at power up is undetermined. Therefore at least 1 L –>H transition on SYNC is required to set M2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| THS8133TQFP | TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION |
| THS8134ATQFP | TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION |
| THS8134BTQFP | TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION |
| THS8134TQFP | TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION |
| THX15C | 14 pin DIP, 5.0 Volt, HCMOS/TTL, Clock Oscillator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS8133B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION |
| THS8133BCPGP | 制造商:Texas Instruments 功能描述: |
| THS8133BCPHP | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 10B 80 MSPS Triple Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| THS8133BCPHPG4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION |
| THS8133BEVM | 制造商:Texas Instruments 功能描述:THS8133B TRIPLE 10BIT 80MSPS VID DAC EVM - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。