參數(shù)資料
型號(hào)： THS8133ATQFP
廠商： Texas Instruments, Inc.
英文描述： TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
中文描述： 三路10位，80 MSPS的視頻D /與Tri轉(zhuǎn)爐電平同步發(fā)電
文件頁(yè)數(shù)： 3/23頁(yè)
文件大小： 339K
代理商： THS8133ATQFP
THS8133, THS8133A, THS8133B
TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
RPr0–PRr9
PIN
13–22
I
Red or Pr pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for different
operating modes
SYNC
24
I
Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output
(INS3_INT=L, see terminal M2) or ARPr, AGY and ABPb outputs (INS3_INT=H, see terminal M2) are driven to
the sync level, irrespective of the values on the data or BLANK inputs. Consequently, SYNC should remain low
for the whole duration of sync, which is in the case of a tri-level sync both the negative and positive portion (see
Figure 7).
SYNC_T
25
I
Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted, a positive sync (higher
than blanking level) is generated when SYNC is low. When disabled, a negative sync (lower than blanking level)
is generated when SYNC is low. When generating a tri-level (negative-to-positive) sync, a L
→
H transition on
this signal positions the start of the positive transition. See Figure 6 for timing control.
The value on SYNC_T is ignored when SYNC is not asserted (high).
VREF
37
I/O
Voltage reference for DACs. An internal voltage reference of nominally 1.35 V is provided, which requires an
external 0.1
μ
F ceramic capacitor between VREF and AVSS. However, the internal reference can be overdriven
by an externally supplied reference voltage.
R/Pr
Register
ARPr
RPr[9:0]
DAC
G/Y
Register
B/Pb
Register
DAC
DAC
DVDD
Configuration
Control
SYNC/BLANK
Control
Bandgap
Reference
GY[9:0]
BPb[9:0]
CLK
M1
M2
AGY
ABPb
DVSS
COMP
VREF
AVDDAVSS
SYNC
BLANK
FSADJ
SYNC_T
Input
Formatter
Figure 1. THS8133 Block Diagram
相關(guān)PDF資料
PDF描述
THS8133TQFP TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
THS8134ATQFP TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
THS8134BTQFP TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
THS8134TQFP TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THS8133B 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION
THS8133BCPGP 制造商:Texas Instruments 功能描述:
THS8133BCPHP 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 10B 80 MSPS Triple Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray
THS8133BCPHPG4 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION
THS8133BEVM 制造商:Texas Instruments 功能描述:THS8133B TRIPLE 10BIT 80MSPS VID DAC EVM - Bulk
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