參數(shù)資料
型號(hào): THS8135PHPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
封裝: GREEN, PLASTIC, HTQFP-48
文件頁數(shù): 4/25頁
文件大?。?/td> 522K
代理商: THS8135PHPG4
THS8135
TRIPLE 10BIT, 240 MSPS VIDEO DAC WITH TRILEVEL SYNC AND VIDEO
(ITUR.BT601)COMPLIANT FULL SCALE RANGE
SLAS343A MAY 2001 REVISED JUNE 2002
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
350
450
550
650
750
850
950
1050
1150
1250
1350
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8 7.3
1450
Output
V
oltage
mV
OUTPUT VOLTAGE
vs
FULL-SCALE RESISTANCE
R(FS) Full-Scale Resistance k
V
O
Full-Scale DAC Output
Current Adjustment at
37.5-
DAC Termination
Figure 5. Vout vs RFS
The user is free to connect another resistor value, but care should be taken not to exceed the maximum current
level on each of the DAC outputs as shown in the specifications section.
backward compatibility with the THS8133
power supply
The THS8135 is a functional superset to the THS8133 and is footprint compatible i.e. a board designed for the
THS8133 can also be used with the THS8135. Both devices come in the same package and have identical
pinouts. Only the power supply levels need to be adjusted as shown in Table 7.
Table 7. Power Supply Changes THS8133 vs THS8135
THS8133
THS8135
AVDD
5 V
3.3 V
DVDD
3.3 V to 5 V
1.8 V
device configuration
The THS8135 samples both M1 and M2 on the second rising edge of CLK after a transition on SYNC in video
modes. Depending on the polarity of the transition, M1 is interpreted as either M1_INT or BLK_INT. In the
THS8133 the M1 signal is not sampled but continuously interpreted, and is only interpreted as M1_INT. The
THS8133 does not offer a reduced-scale input code range configuration and therefore does not require
BLNK_INT.
Only when this additional functionality, which is typical for video systems, is desired, a small change in the
configuration of the device is required by supplying a dynamically changing signal on M1, generated in a similar
way as M2, as shown in Table 8.
Note that this backward compatibility is due to the selection of full-scale versus reduced-scale configurations
in Table 5. All configurations that have equal logic levels for BLNK_INT and M1_INT produce full-scale input
code range, which are compatible with the THS8133. This allows the use of a signal tied high or low on M1, as
on the THS8133, for these backward compatible full-scale configurations.
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