參數(shù)資料
型號(hào): THS8135PHPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
封裝: GREEN, PLASTIC, HTQFP-48
文件頁數(shù): 5/25頁
文件大小: 522K
代理商: THS8135PHPG4
THS8135
TRIPLE 10BIT, 240 MSPS VIDEO DAC WITH TRILEVEL SYNC AND VIDEO
(ITUR.BT601)COMPLIANT FULL SCALE RANGE
SLAS343A MAY 2001 REVISED JUNE 2002
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
DAC outputs
The position of the blanking levels in the THS8135 differs from the position of the blanking levels in the THS8133.
This is to accommodate both full- and reduced-scale configurations on this device, while the THS8133 only
supported full-scale. When the DAC output is ac-coupled, as is typically the case, there is no change to the
output video waveform. Typically a clamp circuit at the receiving side will restore the signal to the proper dc level.
video DAC vs generic DAC modes
The THS8133 does not offer a generic DAC mode. The THS8135 uses only the same number of control signals
than the THS8133 but additionally introduces a generic video mode by specific use of a don’t care signal
combination of these control signals on the THS8133.
programming example for M22
Configuration of the device is normally static in a given application, although it is theoretically possible to
reconfigure the device during operation.
If M2_INT and INS3_INT need to be either low or high, the M2 pin is simply tied low or high. If M2_INT and
INS3_INT need to have different levels, these can be easily derived from the signal on the SYNC pin, as shown
in Table 8 and Figure 6.
Table 8. Generating M2 From SYNC
IN ORDER TO HAVE:
M2_INT
INS3_INT
APPLY TO M2:
L
H
... SYNC delayed by two CLK periods
H
L
... inverted SYNC delayed by two CLK periods
M1 can be generated similarly. Therefore, at most one inverter and two flip flops are needed to configure any
of the THS8135 modes using M1 and M2.
CLK
SYNC
M2
(= SYNC_delayed)
INS3_INT
M2_INT
M2
(= Not SYNC_delayed)]
INS3_INT
M2_INT
if (M2 = SYNC_delayed)
→ M2_INT = L and INS3_INT = H
if (M2 = NOT SYNC_delayed)
→ M2_INT = H and INS3_INT = L
Figure 6. Generating INS3_INT and M2_INT From M2
2Programming M1 is analogous.
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