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參數(shù)資料
| 型號： | Tiny12 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-bit AVR Microcontroller with 1K Byte Flash |
| 中文描述： | 8位AVR微控制器，帶有1K字節(jié)閃存 |
| 文件頁數(shù)： | 83/91頁 |
| 文件大?。?/td> | 1137K |
| 代理商： | TINY12 |
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83
ATtiny11/12
1006D–AVR–07/03
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
ADC
Rd, Rr
SUB
Rd, Rr
SUBI
Rd, K
SBC
Rd, Rr
SBCI
Rd, K
AND
Rd, Rr
ANDI
Rd, K
OR
Rd, Rr
ORI
Rd, K
EOR
Rd, Rr
COM
Rd
NEG
Rd
SBR
Rd,K
CBR
Rd,K
INC
Rd
DEC
Rd
TST
Rd
CLR
Rd
SER
Rd
BRANCH INSTRUCTIONS
RJMP
k
RCALL
k
RET
RETI
CPSE
Rd,Rr
CP
Rd,Rr
CPC
Rd,Rr
CPI
Rd,K
SBRC
Rr, b
SBRS
Rr, b
SBIC
P, b
SBIS
P, b
BRBS
s, k
BRBC
s, k
BREQ
k
BRNE
k
BRCS
k
BRCC
k
BRSH
k
BRLO
k
BRMI
k
BRPL
k
BRGE
k
BRLT
k
BRHS
k
BRHC
k
BRTS
k
BRTC
k
BRVS
k
BRVC
k
BRIE
k
BRID
k
Add two Registers
Add with Carry two Registers
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Rd
←
Rd + Rr
Rd
←
Rd + Rr + C
Rd
←
Rd - Rr
Rd
←
Rd - K
Rd
←
Rd - Rr - C
Rd
←
Rd - K - C
Rd
←
Rd
Rr
Rd
←
Rd
K
Rd
←
Rd v Rr
Rd
←
Rd v K
Rd
←
Rd
⊕
Rr
Rd
←
$FF - Rd
Rd
←
$00 - Rd
Rd
←
Rd v K
Rd
←
Rd
(FFh - K)
Rd
←
Rd + 1
Rd
←
Rd - 1
Rd
←
Rd
Rd
Rd
←
Rd
⊕
Rd
Rd
←
$FF
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Relative Jump
Relative Subroutine Call
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
PC
←
PC + k + 1
PC
←
PC + k + 1
PC
←
STACK
PC
←
STACK
if (Rd = Rr) PC
←
PC + 2 or 3
Rd - Rr
Rd - Rr - C
Rd - K
if (Rr(b)=0) PC
←
PC + 2 or 3
if (Rr(b)=1) PC
←
PC + 2 or 3
if (P(b)=0) PC
←
PC + 2 or 3
if (P(b)=1) PC
←
PC + 2 or 3
if (SREG(s) = 1) then PC
←
PC + k + 1
if (SREG(s) = 0) then PC
←
PC + k + 1
if (Z = 1) then PC
←
PC + k + 1
if (Z = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (N = 1) then PC
←
PC + k + 1
if (N = 0) then PC
←
PC + k + 1
if (N
⊕
V= 0) then PC
←
PC + k + 1
if (N
⊕
V= 1) then PC
←
PC + k + 1
if (H = 1) then PC
←
PC + k + 1
if (H = 0) then PC
←
PC + k + 1
if (T = 1) then PC
←
PC + k + 1
if (T = 0) then PC
←
PC + k + 1
if (V = 1) then PC
←
PC + k + 1
if (V = 0) then PC
←
PC + k + 1
if ( I = 1) then PC
←
PC + k + 1
if ( I = 0) then PC
←
PC + k + 1
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2
3
4
4
1/2
1
1
1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
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