參數(shù)資料
型號: TLV1571IPWLE
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
文件頁數(shù): 2/26頁
文件大?。?/td> 388K
代理商: TLV1571IPWLE
TL
V1571,
TL
V1578
2.7
V
to
5.5
V
,1-/8-CHANNEL,
10-BIT
,
RARALLEL
ANALOG-T
O-DIGIT
AL
CONVERTERS
SLAS170A
MARCH
1999
REVISED
AUGUST
1999
10
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
internal clock
In single channel input mode, with CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and
conversion begins at the rising edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after
each conversion.
OR
Auto Powerdown
CS
WR
CSTART
INTCLK
RD
D[0:9]
INT
EOC
Config
Data
ADC
Data
ADC
Data
t
su(CSL_WRL)
t
h(WRH_CSH)
t
d(CSH_CSTARTL)
t
SAMPLE
t
su(DAV_WRH)
t
h(WRH_DAV)
t
CONV
t
su(CSL_RDL)
t
h(RDH_CSH)
t
en(RDL_DAV)
t
dis(RDH_DAV)
t
CONV
t
su(CSL_RDL)
t
en(RDL_DAV)
t
STARTOSC
t
STARTOSC
9
10
1
0
Auto Powerdown
Figure 5. Single Channel Input Mode Conversion – Hardware CSTART, Internal Clock
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