參數資料
型號: TLV1571IPWLE
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
文件頁數: 3/26頁
文件大?。?/td> 388K
代理商: TLV1571IPWLE
TL
V1571,
TL
V1578
2.7
V
T
O
5.5
V
,1-/8-CHANNEL,
10-BIT
,
P
ARALLEL
ANALOG-T
O-DIGIT
AL
CONVERTERS
SLAS170A
–MARCH
REVISED
AUGUST
1999
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
11
software START conversion
external clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks
after sampling begins. At the end of conversion, the EOC pulse goes low then high telling the host that conversion is ready to be read out.
The external clock is active and used as the reference at all times. With this mode, WR and RD should not be applied at the rising edge of
the clock (see Figure 3).
Auto Powerdown
CLK
CS
WR
RD
D[0:9]
INT
EOC
Config
Data
ADC Data
t
su(CSL_WRL)
t
h(WRH_CSH)
t
su(DAV_WRH)
t
h(WRH_DAV)
t
CONV
t
su(CSL_RDL)
t
h(RDH_CSH)
t
en(RDL_DAV)
t
dis(RDH_DAV)
t
CONV
t
en(RDL_DAV)
01
5
6
7
15
16
OR
su(CSL_RDL)
Figure 6. Single Channel Input Mode Conversion – Software Start, External Clock
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