參數(shù)資料
型號(hào): TLV2556IPW
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁(yè)數(shù): 24/37頁(yè)
文件大?。?/td> 729K
代理商: TLV2556IPW
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
30
www.ti.com
PRINCIPLES OF OPERATION
bipolar output format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared
to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result
of an input voltage equal to or less than VREF– is a code with all zeros (000 . . . 0) and the conversion result of
an input voltage equal to or greater than VREF+ is a code of all ones (111 . . . 1). The conversion result of (VREF+
+ VREF–)/2 is a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100 . . . 0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones
(011 . . . 1). The conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted
as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s
complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
reference
The device has a built-in reference with a programmable level of 2.048 V or 4.096 V. If the internal reference
is used, REF+ is set to 2.048 V or 4.096 V and REF– is set to analog GND. An external reference can also be
used through two reference input pins, REF+ and REF–, if the reference source is programmed as external.
The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a
full-scale and zero-scale reading respectively. The values of REF+, REF–, and the analog input should not
exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The
digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input
signal is equal to or lower than REF–.
相關(guān)PDF資料
PDF描述
TLV2556IDWR 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLV2556IPWR 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLV2556IDW 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLV2556IPWG4 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLV2556MPWREP 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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