參數(shù)資料
型號(hào): TLV2556IPWR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁數(shù): 17/37頁
文件大?。?/td> 729K
代理商: TLV2556IPWR
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
24
www.ti.com
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Pad
Zeros
1
2
3
5
4
610
11
12
1
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
MSB–8 MSB–9 LSB+1
LSB
Hi–Z State
D6
D5
D4
D3
D2
D1
D0
D7
8
7
9
MSB–6 MSB–7
D7
MSB
16
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
tconv
Previous Conversion Data
Initialize
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
INT
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 50. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
Pad
Zeros
MSB
1
2
3
5
4
610
11
12
1
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
MSB–8 MSB–9 LSB+1
LSB
16
8
7
9
MSB–6 MSB–7
Low Level
MSB
D6
D5
D4
D3
D2
D1
D0
D7
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
Previous Conversion Data
Initialize
CS
I/O
CLOCK
DATA
OUT
DATA IN
EOC
INT
tconv
Initialize
Figure 51. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
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