參數(shù)資料
型號： TLV2556IPWR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： GREEN, PLASTIC, TSSOP-20
文件頁數(shù)： 18/37頁
文件大?。?/td> 729K
代理商： TLV2556IPWR
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
25
www.ti.com
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
DATA OUT
1
2
3
5
4
610
11
12
1
I/O CLOCK
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
MSB–8 MSB–9 LSB+1
LSB
Hi–Z State
DATA IN
8
7
9
MSB–6 MSB–7
D7
MSB
16
EOC
Initialize
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
Access Cycle
Sample Cycle
CS
Previous Conversion Data
Pad Zeros
Channel
Address
Output Data
Format
A/D Conversion Interval
tconv
DATA IN Can be Tied or Held High
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 52. Timing for Default Mode Using CS: (16-Clock Transfer, MSB First, Ext. Ref,
Pin 19 = EOC, Input = AIN0)
Access Cycle
Sample Cycle
MSB
DATA OUT
1
2
3
5
4
610
11
12
1
I/O CLOCK
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
MSB–8 MSB–9 LSB+1
LSB
16
DATA IN
8
7
9
MSB–6 MSB–7
Low Level
MSB
D7
EOC
Initialize
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
Previous Conversion Data
Pad Zeros
Channel
Address
Output Data
Format
A/D Conversion Interval
tconv
DATA IN Can be Tied or Held High
CS
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 53. Timing for Default Mode Not Using CS: (16-Clock Transfer, MSB First Ext. Ref,
Pin 19 = EOC, Input = AIN0)
To remove the device from default mode, CFGR2–D0 must be reset to 0. Valid sample/convert cycles can
resume on the cycle following the CFGR2 configuration.
相關(guān)PDF資料
PDF描述
TLV2556IDW 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLV2556IPWG4 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLV2556MPWREP 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLV2556MPWREPG4 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
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