SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
Low-Power Stereo ADC With Embedded miniDSP
for Wireless Handsets and Portable Audio
1
FEATURES
2,24-mm
× 2,16-mm NanoFree 16-Ball
16-YZH Wafer Chip Scale Package (WCSP)
234
Stereo Audio ADC
– 92-dBA Signal-to-Noise Ratio
APPLICATIONS
– Supports ADC Sample Rates From 8 kHz to
Wireless Handsets
96 kHz
Portable Low-Power Audio Systems
Instruction-Programmable Embedded miniDSP
Noise Cancellation Systems
Flexible Digital Filtering With RAM
Front-End Voice or Audio Processor for Digital
Programmable Coefficient, Instructions, and
Audio
Built-In Standard Modes
– Low-Latency IIR Filters for Voice
DESCRIPTION
– Linear Phase FIR Filters for Audio
The TLV320ADC3001 is a low-power, stereo audio
– Additional Programmable IIR Filters for EQ,
analog-to-digital converter (ADC) supporting sampling
Noise Cancellation, or Reduction
rates from 8 kHz to 96 kHz with an integrated
programmable-gain amplifier providing up to 40 dB
– Up to 128 Programmable ADC Digital Filter
analog gain or AGC. A programmable miniDSP is
Coefficients
provided for custom audio processing. Front-end
Three Audio Inputs With Configurable
input coarse attenuation of 0 dB,
–6 dB, or off, is also
Automatic Gain Control (AGC)
provided.
The
inputs
are
programmable
in
a
– Programmable in Single-Ended or Fully
combination
of
single-ended
or
fully
differential
configurations.
Extensive
register-based
power
Differential Configurations
control is available via I2C, enabling mono or stereo
– Can Be Driven Hi-Z for Easy Interoperability
recording.
Low
power
consumption
makes
the
With Other Audio ICs
TLV320ADC3001 ideal for battery-powered portable
Low Power Consumption and Extensive
equipment.
Modular Power Control:
The AGC programs to a wide range of attack
– 6-mW Mono Record 8-kHz
(7 ms
–1.4 s) and decay (50 ms–22.4 s) times. A
– 11-mW Stereo Record, 8-kHz
programmable noise gate function is included to
avoid noise pumping. Low-latency IIR filters optimized
– 10-mW Mono Record, 48-kHz
for voice and telephony are available, as well as
– 17-mW Stereo Record, 48-kHz
linear-phase
FIR
filters
optimized
for
audio.
Programmable Microphone Bias
Programmable IIR filters are also available and may
be used for sound equalization, or to remove noise
Programmable PLL for Clock Generation
components.
The
audio
serial
bus
can
be
I2C
Control Bus
programmed
to
support
I2S,
left-justified,
Audio Serial Data Bus Supports I2S,
right-justified, DSP, PCM, and TDM modes. The
Left/Right-Justified, DSP, PCM, and TDM
audio bus may be operated in either master or slave
Modes
mode.
Power Supplies:
A programmable integrated PLL is included for
flexible clock generation and support for all standard
– Analog: 2.6 V–3.6 V.
audio rates from a wide range of available MCLKs,
– Digital: Core: 1.65 V–1.95 V,
varying from 512 kHz to 50 MHz, including the most
I/O: 1.1 V
–3.6 V
popular
cases
of
12-MHz,
13-MHz,
16-MHz,
19.2-MHz, and 19.68-MHz system clocks.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoFree, PurePath Studio are trademarks of Texas Instruments.
3
I2C is a trademark of NXP B.V.
4
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright
2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.