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參數(shù)資料
| 型號(hào)： | TLV2556MPWREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 20/37頁 |
| 文件大?。?/td> | 705K |
| 代理商： | TLV2556MPWREPG4 |
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PRINCIPLES OF OPERATION
Converter Operation
Data I/O Cycle
Sampling Period
Conversion Cycle
www.ti.com ................................................................................................................................................... SLAS598A – NOVEMBER 2008 – REVISED JULY 2009
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). There are two sets of configuration
registers, configuration register 1 – CFGR1 and configuration register 2 – CFGR2. CFGR1, which controls output
data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB first bit (D1), and
a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN) except for command
1111b. CFGR2, which provides configuration information other than data format, consists of a 2-bit reference
select (D3–D2), an EOC/INT program bit (D1), and a default mode select bit (D0) that are applied to command
1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data
register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output
data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long depending
on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling
edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The
last falling edge of the I/O CLOCK sequence also takes EOC low (if pin 19 = EOC) and begins the conversion.
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the
sampling cycle, and 3) the conversion cycle. The first two are partially overlapped.
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to
DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. Data input is
ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12, or
16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after the
four address/command bits have been clocked into the input data register. Sampling starts on the fourth falling
edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling
edge of I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high or INT goes low (indicating that the conversion is complete) to maximize the sampling accuracy and
minimize the influence of external digital noise.
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns) to
start the OSC. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage.
When programmed as EOC, pin 19 goes low at the start of the conversion cycle and goes high when the
conversion is complete and the output data register is latched. After EOC goes low, the analog input can be
changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to
the falling edge of EOC is fixed, any time-varying analog input signals can be digitized at a fixed rate without
introducing systematic harmonic distortion or noise due to timing uncertainty.
Copyright 2008–2009, Texas Instruments Incorporated
27
Product Folder Link(s): TLV2556-EP
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