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參數(shù)資料
| 型號： | TLV2556MPWREPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 21/37頁 |
| 文件大?。?/td> | 705K |
| 代理商： | TLV2556MPWREPG4 |
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Power Up and Initialization
Default Mode
Data Input
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
When programmed as INT, pin 19 goes low when the conversion is complete and the output data register is
latched. The next I/O CLOCK rising edge clears the INT output. The time from the last I/O CLOCK falling edge to
the falling INT edge is equivalent to the EOC delay mentioned above plus the maximum conversion time. INT is
cancelled by (or brought to high) by either the next CS falling edge or the next SCLK rising edge (when CS is
held low all of the time for multiple cycles). When CS is held low continuously (for multiple cycles) MSB output
occurs after the first rising edge of I/O CLOCK after EOC is inactive or the falling edge of INT.
After power up, CS must be taken from high to low to begin an I/O cycle. INT/EOC pin is initially high, and both
configuration registers are set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to
begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not
read accurately due to internal device settling.
Table 1. Operational Terminology
The entire I/O CLOCK sequence that transfers address and control data into the data register and
Current (N) I/O cycle
clocks the digital result from the previous conversion from DATA OUT.
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is
Current (N) conversion cycle
the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into
the output register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle
The conversion cycle just prior to the current I/O cycle
Next (N+1) I/O cycle
The I/O period that follows the current conversion cycle
Example
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
When the DATA IN pin is held high, the ADC goes into hardware default mode because the CFGR2 bits are all
programmed to the default values after eight I/O CLOCK cycles. This means the ADC is programmed for an
external reference and pin 19 as EOC. In addition, channel AIN0 is selected. The first conversion is invalid
therefore the conversion result should be ignored. On the next cycle, AIN0 is sampled and converted. This mode
of operation is valid when CS is toggled or held low after the first cycle.
To remove the device from hardware default mode, CFGR2 bit D0 must be reset to 0. Once this is done, the host
must program CFGR1 on the next cycle and disregard the result from the current cycle’s conversion.
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
28
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2556-EP
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