參數(shù)資料
型號： TLV320A11IPFBG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁數(shù)： 19/55頁
文件大?。?/td> 263K
代理商： TLV320A11IPFBG4
2–12
2.7.5
Frame-Sync Delayed (FSD) Function, Cascade Mode
In cascade mode, the DSP must be able to identify the master and slaves according to the register map shown in
Appendix A. Each device in the cascade contains a 3-bit cascade register (D15-D13 in the register address) that has
been programmed by the ACD (automatic cascade detection) with an address value equal to its position in the
cascade during the device’s power-up initialization (see Section 2.1.11). The device address of the master is always
equal to the number of slaves in the cascade. For example, in Figure 2–15, D15-D13 of the master will be 011, as
shown in row 4 of Table A-1 (Appendix A). The DSP receives all frame-sync pulses from the master though the
master’s FS. The master FSD is output to the first slave, and the first slave FSD is output to the second slave device,
and so on. Figure 2–15 shows the cascade of 4 TLV320AIC11s in which the closest one to the DSP is the master,
and the rest are slaves. The FSD output of each device is input to the FS terminal of the succeeding device.
Figure 2–16 shows the FSD timing sequence in the cascade.
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
Slave 2
Slave 1
Slave 0
Master
MCLK
DIN
DOUT
FSD
SCLK
FSD
FS
CLKOUT
DX
DR
FSX
FSR
CLKX
CLKR
TMS320UC54x
DVDD
FSD
M/S
(or Master Clock Source)
DVDD
1 k
Figure 2–15. Cascade Mode Connection (to DSP Interface)
M
32 SCLKs
Master FS
P
S2
P
S1
P
S0
P
M
S
S2
S
Master FSD,
Slave 2 FS
Slave 2 FSD,
Slave 1 FS
Slave 1 FSD,
Slave 0 FS
Slave 0 FSD
(See Note)
32 SCLKs
NOTE: Slave 0 FSD should be left open.
Figure 2–16. Master-Slave Frame-Sync Timing
相關(guān)PDF資料
PDF描述
TLV320AIC11IPFBG4 SPECIALTY CONSUMER CIRCUIT, PQFP48
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