參數(shù)資料
型號(hào)： TLV320A11IPFBG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁(yè)數(shù)： 8/55頁(yè)
文件大小： 263K
代理商： TLV320A11IPFBG4
2–2
Figure 2–1. Timing Sequence of ADC Channel (Primary Communication Only)
FS
DOUT
(16-bit)
DOUT
(15+1-bit)
Primary
Secondary
16 SCLKs
# SCLKs Per Sampling Period (See Note C)
16–bit ADC Data
15–bit ADC Data + M/S
M/S+ Register Data/
M/S+ All 0 (See Note A)
# SCLKs (See Note B)
M/S+ Register Data/
M/S+ All 0 (See Note A)
Primary
16 SCLKs
NOTES: A. M/S bit (D15) in the secondary communication is used to indicate whether the register data (address and content) come from a
master device or a slave device if read bit is set. Otherwise, it is all 0s except M/S bit (master: M/S=1, slave: M/S=0).
B. The number of SCLKs between FS (primary) and FS (secondary) is 128 if cascading devices are less than 5, or 256 if cascading
devices are greater than 4.
C. The number of SCLKs per data sampling period is 256 if cascading devices are less than 5, or 512 if cascading devices are greater
than 4.
Figure 2–2. Timing Sequence of ADC Channel (Primary and Secondary Communication)
2.1.3
DAC Signal Channel
DIN received the 16-bit serial data word (2s complement) from the host during the primary communication interval.
These 16-bit digital words, representing analog output signal before PGA, are clocked into the serial port (DIN) at
the falling edge of SCLK during the frame-sync interval, one bit for each SCLK and one word for each primary
communication interval. The data are converted to a pulse train by the sigma-delta DAC comprised of a
digital-interpolation filter and a digital 1-bit modulator. The output of the modulator is then passed to an internal
low-pass filter to complete the signal reconstruction. Finally, the resulting analog signal is applied to the input of a
programmable-gain amplifier is capable of differentially driving a 600-ohm load at OUTP and OUTM. The timing
sequence is shown in Figure 2–3.
During secondary communication, the digital control and configuration data, together with the register address, are
clocked in through DIN (see Appendix A for register map). These 16-bit data are used either to initialize the register
or read out register content through DOUT. If a register initialization is not required, a no-operation word (D15-D9 are
all set to 0) can be used. If D12 is set to 1, the content of the control register, specified by D7-D0, will be sent out
through DOUT during the same secondary communication (see section 2.1.5). The timing sequence is shown in
Figure 2–4.
The interpolation FIR filter can be bypassed by writing a 1 to bit D1 of control register 1. The whole DAC channel can
be turned off for power savings by writing 10 to bits D2 and D1 of control register 3.
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