參數(shù)資料
型號： TLV320AIC13C
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO30
封裝： PLASTIC, SOP-30
文件頁數(shù)： 18/55頁
文件大?。?/td> 455K
代理商： TLV320AIC13C
3–12
3.8.1
Programming Mode
In the programming mode, the FS signal starts the input/output data stream. Each period of FS contains two frames
as shown in Figures 3–14 and 3–15: data frame and control frame. The data frame contains data transmitted from
the ADC or to the DAC. The control frame contains data to program the AIC13s control registers. The SMARTDM
automatically sets the number of time slots per frame equal to 2 times the number of AIC13 codecs in the interface.
Each time slot contains 16-bit data. The SCLK is used to perform data transfer for the serial interface between the
AIC13 codecs and the DSP. The frequency of SCLK varies depending on the selected mode of serial interface. In
the stand alone-mode, there are 32 SCLKs (or two time slots) per sampling period. In the master-slave cascade
mode, the number of SLCKs equals 32x(Number of codecs in the cascade). The digital output data from the ADC
is taken from DOUT. The digital input data for the DAC is applied to DIN. The synchronization clock for the serial
communication data and the frame-sync is taken from SCLK. The frame-sync signal that starts the ADC and DAC
data transfer interval is taken from FS. The SMARTDM also provides a turbo mode, in which the FS’s frequency is
always the device’s sampling frequency, but SCLK is running at a much higher speed. Thus, there are more than 32
SCLKs per sampling period, in which the data frame and control frame occupy only the first 32 SCLKs from the falling
edge of the frame-sync FS (also see Section 3.6 for more details).
SCLK
FS
DIN
DOUT
16–Bit DAC Data
Register Data Write
16–Bit ADC Data
Register Data Read
Slot Number 0
Slot Number 1
Figure 3–14. Standard Operation/Programming Mode: Stand-Alone Timing
SCLK
FS
DIN/
DOUT
0
12
2n–1
2n–2
2n–3
Master Slave
n–2
Slave
n–3
Slave
2
Slave
1
Slave
0
Master Slave
n–2
Slave
n–3
Slave
2
Slave
1
Slave
0
Data Frame
Control Frame
(Register R/W)
16 SCLKs Per Slot
Slot
Number
NOTE: n is the total number of AIC13s in the cascade
Figure 3–15. Standard Operation/Programming Mode: Master-Slave Cascade Timing
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PDF描述
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