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參數(shù)資料
| 型號： | TLV320AIC14I |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO30 |
| 封裝： | PLASTIC, TSSOP-30 |
| 文件頁數(shù)： | 11/54頁 |
| 文件大小： | 450K |
| 代理商： | TLV320AIC14I |
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3–6
3.6.3
Serial Data In (DIN)
The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of FS. In a data
frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is used, the LSB (D0) is
set to 1 to switch from the continuous data transfer mode to the programming mode. In a control frame, the data is
the control and configuration data that sets the device for a particular function as described in Section 3.9, Control
Register Programming.
3.6.4
Frame-Sync FS
The frame-sync signal (FS) indicates the device is ready to send and receive data. FS is an output if the M/S pin is
connected to HI (master mode) and an input if the M/S pin is connected to LO (slave mode).
Data is valid on the falling edge of the FS signal.
The frequency of FS is defined as the sampling rate of the TLV320AIC14 and derived from the master clock MCLK
as followed (see Section 3.1 Operating Frequencies for details):
FS = MCLK / (16
× P × N × M)
SCLK
FS
DIN/DOUT
(16 Bit)
MSB
LSB
D15
D14
D2
D1
0
1
15
16
14
D0
16 SCLKs
Figure 3–5. Timing Diagram of FS
3.6.5
Cascade Mode and Frame-Sync Delayed (FSD)
In cascade mode, the DSP receives all frame-sync pulses from the master though the master’s FS. The master’s FSD
is output to the first slave and the first slave’s FSD is output to the second slave device and so on. Figure 3–7 shows
the cascade of 4 TLV320AIC14s in which the closest one to DSP is the master and the rest are slaves. The FSD output
of each device is input to the FS terminal of the succeeding device. Figure 3–8 shows the FSD timing sequence in
the cascade.
3.6.6
Stand-Alone Slave
In the stand-alone slave connection, the FS and SCLK are input in which they need to be synchronized to each other
and programmed according to Section 3.1 (Operating Frequencies). The FS and SCLK input are not required to
synchronize to the MCLK input but must remain active at all times to assure continuous sampling in the data converter.
FS is output for initial 132 MCLK and it must be kept low. DSP needs to keep FS low-or high-impedance state for this
period to avoid contention on FS.
3.6.7
Asynchronous Sampling
(Codecs in cascade are sampled at different sampling frequency)
The AIC14’s SMARTDM support different sampling frequency between the different codecs in cascade connecting
to a single serial port. In this case, all codecs are required to sample at the same fdrequency that is the frequency
of FS signal. Then the desired sampling frequency of each codec is calculated by D2–D0 of control register 3. For
example: fs1 and fs2 are desired sampling rates for CODEC1 and CODEC2 respectively:
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| TLV320AIC14IDBTRG4 | 功能描述:接口—CODEC Lo-Pwr Mono Voice Band CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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