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| 型號(hào)： | TLV320AIC22PT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 24/55頁 |
| 文件大?。?/td> | 782K |
| 代理商： | TLV320AIC22PT |
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TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
sampling rate mode 2 (continued)
Table 10. I, N, and D Derivation for Various Sample Rates, With MCLK = 24.576 MHz
I, N, AND D VALUES FOR CHANNEL SAMPLE RATES, WITH
MCLK = 24.576 MHz
ACTUAL VALUES TO BE
PROGRAMMED IN REGISTERS 1, 2, 6,
AND 7
Channel sample rate (kHz)
I + N/D
I
N
D
I–1
N
D–1
7.2
6.6667
6
4
6
5
4
5
8
6
0
6
5
0
5
8.229
5.833
5
6
4
5
9.6
5
0
6
4
0
5
10.285
4.6669
4
6
3
4
5
12
4
0
6
3
0
5
14.4
3.3333
3
2
6
2
5
16
3
0
6
2
0
5
ADC and DAC channel data
The ADC channel produces 15 bits of 2s-complement conversion data in linear mode or 7 bits of zeros and 8
bits of PCM coded data in A-law or
-law mode, plus a data-valid flag bit which, by default, is enabled. For the
cases where register 12 is programmed for the standard sampling frequencies and the I + N/D divider is not
used, the ADC will place a 1 in the data-valid bit for all conversion data if the data-valid flag is enabled in register
13.
The DAC uses 16 bits of 2s-complement data or 8 bits of zeros, followed by 8 bits of PCM data as input. No
data-valid flag is required for the DAC data.
Based on the rate of the FSYNC pulse, the ADC generates the internal circuit clocks using the (I + N/D) divider.
Two examples below show how different sampling rates are obtained using this technique for sampling rate
mode 2. Both examples are valid for MCLK equal to 32.768 MHz. Note that when FSYNC is not equal to the
sample rate, the valid data is present between several occurrences of invalid data.
Example 1: If an 8-kHz sampling rate is needed and the frame sync rate is at 64 kHz, only one out of every 8th
frame will carry valid data for the codec in its slot. The data-valid flag bit in the data word is used to identify
whether the data is valid (flag bit = 1) or invalid (flag bit = 0). The flag bit is the MSB of the 16-bit data word and
is enabled, by default. The I, N, and D fields are used to decide the setting for the valid bit in the respective data
slot. The codec generates the data-valid flag bits. See Table 11 for I, N, and D derivations for this example.
Table 11. I, N, and D Derivation for 32.768-MHz Clock and 8-kHz Sampling Rate
PARAMETER OR VARIABLE
EQUATION
VALUE
MCLK
None
32.768 MHz (given)
BCLK
MCLK/2
16.384 MHz
FSYNC
BCLK/256
64 kHz
Sample rate
MCLK/(512 x (I + N/D))
8 kHz (given)
I + N/D
MCLK/(512 x sample rate)
8
I
8
N
0
D
9
Example 2: If a 14.4-kHz sampling rate is needed and the frame sync rate is at 64 kHz, then the codec sends
a valid data word every fourth or every fifth frame for 40 frames. This effectively implements I + N/D = 4 + 4/9
to get 14.4 kHz from 64 kHz. The DSP collects the data from every slot in every frame, then checks the data-valid
flag bit. If the flag bit is set, the data is loaded into the buffer, otherwise, it is discarded.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC22PTR | 功能描述:接口—CODEC DUAL VOIP CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STereo Audio CODEC, 8- to 96kHz, With Integrated Headphone Amplifier |
| TLV320AIC23_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier |
| TLV320AIC23B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier |
| TLV320AIC23B_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier |
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