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參數(shù)資料
| 型號： | TLV320AIC22PTR |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | DUAL VOIP CODEC |
| 中文描述： | 雙VoIP編解碼器 |
| 文件頁數(shù)： | 19/55頁 |
| 文件大?。?/td> | 763K |
| 代理商： | TLV320AIC22PTR |
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TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
zero-crossing block
The zero-crossing functionality (programmed in registers 15 and 16) comes into play when the user changes
a preamp or PGA gain setting. When the user wishes to change a gain setting in a particular channel (ADC or
DAC path), the changed gain takes effect when the signal level coming from the particular channel crosses a
programmed threshold. The threshold can be specified in registers 15 and 16 for either channel, for example,
if the user is talking on the handset and wishes to mute it. The zero-crossing block checks the ADC input to see
whether the input falls within the programmed range before making the mute effective internally. This is to avoid
noise if a sharp change is implemented. Note, in the TX path, the zero crossing block checks the ADC input value
only. If both the handset and the microphone are in use with one ADC channel, and the user wishes to mute
the handset only, the zero-crossing block does not avoid noise when muting the handset. If the user mutes both
the handset and the microphone, then zero crossing will be evaluated properly.
On the DAC side, the zero crossing is effective in a similar manner. The DAC output is checked to see whether
the value is within the programmed range. The mute then becomes effective in the driver where mute has been
selected.
Deactivating mute also is taken care of in the same fashion. If the user wants to deactivate mute, the
TLV320AIC22 internally checks to see if the signal level is within the programmed limit and then allows the
device to deactivate. Internally, a change in gain setting becomes effective only after the signal level has
reached a value close to zero.
If the signal does not cross the programmed zero-crossing threshold, the gain change occurs automatically after
64/fs seconds.
channel sampling rates
The TLV320AIC22 can be configured to have standard sampling rates (8 kHz and 16 kHz), or other popular
sampling rates, by loading appropriate registers with a divider to scale the master clock input with an I + N/D
divider. Two modes of operation are discussed below.
D Mode 1 configures the device for the standard sampling rates. In this mode, the sampling rate (fs) equals
the frame sync rate (FSYNC).
D Mode 2 allows user defined sampling rates and uses an (I + N/D) divider.
A block diagram of the clock-division scheme used in the TLV320AIC22 is shown in Figure 10.
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| TLV320AIC23BGQE | 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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