參數(shù)資料
型號： TLV320AIC22PTR
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： DUAL VOIP CODEC
中文描述： 雙VoIP編解碼器
文件頁數(shù)： 21/55頁
文件大?。?/td> 763K
代理商： TLV320AIC22PTR
TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
sampling rate mode 1
Examples of popular master clock frequencies, with the derivations of the sampling rates, bit clocks, and the
frame sync frequencies, are given in Table 7. The default setting is for a case in which the channel sampling
rate and FSYNC are at 8 kHz when a MCLK of 24.576 MHz is provided. The default setting is for register 12
to have bits D6–D4 equal to 000 and registers 1, 2, 6, and 7 to be left in their default configuration.
The various parameters for sampling rate-mode 1 are determined using the following equations:
BCLK = See Table 7
FSYNC = BCLK/256
Sample rate = MCLK/[512(I + N/D)]
Table 7. FSYNC, BCLK, and Sample Rate Derivations With Register Settings
D6
D5
D4
MCLK INPUT
(MHz)
FSYNC
BCLK
SAMPLE RATE
I
N
D
0
24.576
BCLK/256 or 8 kHz
MCLK/12 or 2.048 MHz
MCLK/[512 x (I + N/D)] or 8 kHz
*6
*0
*6
0
1
32.768
BCLK/256 or 8 kHz
MCLK/16 or 2.048 MHz
MCLK/[512 x (I + N/D)] or 8 kHz
8
0
*6
0
1
0
24.576
BCLK/256 or 16 kHz
MCLK/6 or 4.096 MHz
MCLK/[512 x (I + N/D)] or 16 kHz
3
0
*6
0
1
32.768
MCLK/(512x4) or 16 kHz
MCLK/8 or 4.096 MHz
MCLK/[512 x (I + N/D)] or 16 kHz
4
0
*6
This is the default setting.
sampling rate mode 2
In mode 2, the sampling rate for each channel is derived by the noninteger-divide (I + N/D) of the FSYNC signal.
Each channel has dedicated 4-bit programmable fields (I, N, and D) to achieve this. All sampling rates of interest
such as 7.2 kHz, 8 kHz, 8.229 kHz, 9.6 kHz, 10.285 kHz, 12 kHz, and 14.4 kHz, are achievable by programming
the appropriate values into the I, N, and D registers. Register 12 also must be programmed with a decimal value
of 5, 6, or 7 in bits D6 through D4.
The various parameters for sampling rate-mode 2 are determined using the following equation:
BCLK = MCLK/2
FSYNC = BCLK/256
Sample rate = MCLK/[512 x (I + N/D)]
BCLK is generated by the master codec according to the following relationship (note that MCLK is 32.768 MHz
for this example):
BCLK = MCLK/2 = 32.768 MHz/2 = 16.384 MHz
and the FSYNC is obtained by dividing the BCLK by 256:
FSYNC = BCLK/256 = 16.384 MHz/256 = 64 kHz
An example of how to achieve a channel sample rate of 12 kHz with an MCLK of 32.768 MHz is shown in Table 8.
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