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參數(shù)資料
| 型號(hào)： | TLV320AIC24I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Layout and Grounding Guidelines for TLV320AIC2x |
| 中文描述： | 為TLV320AIC2x布局和接地指南 |
| 文件頁數(shù)： | 5/46頁 |
| 文件大?。?/td> | 452K |
| 代理商： | TLV320AIC24I |
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SLAS428 AUGUST 2004
www.ti.com
5
ELECTRICAL CHARACTERISTICS
At +25
°
C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. Vref = 2.5 V, Fs (Audio) = 48 kHz, unless otherwise noted (continued)
PARAMETER
TEST CONDITIONS
VOLTAGE REFERENCE
VREF output programmed as 2.5 V
VREF output programmed as 1.25 V
MIN
TYP
MAX
UNITS
Voltage range
2.3
2.5
2.7
V
1.15
1.25
1.35
Voltage range
External VREF. By design, not tested in
production.
1.2
2.55
V
Reference drift
Internal VREF = 1.25 V
29
ppm/
°
C
Current drain
Extra current drawn when the internal
reference is turned on.
650
μ
A
DIGITAL INPUT / OUTPUT(1)
Internal clock frequency
8.8
MHz
Logic family
CMOS
Logic level:
VIH
VIL
VOH
VOL
IIH = +5
μ
A
IIL = +5
μ
A
IOH = 2 TTL loads
IOL = 2 TTL loads
0.7xIOVDD
V
0.3
0.3xIOVDD
V
0.8xIOVDD
V
0.1xIOVDD
V
Capacitive load
10
pF
POWER SUPPLY REQUIREMENTS
Power supply voltage
AVDD(2)
DRVDD(2)
2.7
3.6
V
2.7
3.6
V
IOVDD
1.1
3.6
V
DVDD
1.525
1.95
V
IAVDD
48 ksps, output drivers in low
off
2.2
Stereo audio playback
IDRVDD
0
mA
IDVDD
power mode, VGND off, PLL
2.4
IAVDD
Additional power consumed
when PLL is enabled.
0.1
PLL
IDRVDD
1.3
mA
IDVDD
0.9
IAVDD
Additional power consumed
when VGND is powered.
0.3
VGND
IDRVDD
0.9
mA
IDVDD
0
Hardware power down
(1)Internal oscillator is designed to give nominally 8-MHz clock frequency. However, due to process variations, this frequency can vary from device
to device. All calculations for delays and wait times in the data sheet assume an 8-MHz oscillator clock.
(2)It is recommended that AVDD and DRVDD be set to the same voltage for the best performance. It is also recommended that these supplies be
separated on the user’s PCB.
All currents
2
μ
A
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