參數(shù)資料
型號: TLV320AIC24I
廠商: Texas Instruments, Inc.
英文描述: Layout and Grounding Guidelines for TLV320AIC2x
中文描述: 為TLV320AIC2x布局和接地指南
文件頁數(shù): 9/46頁
文件大?。?/td> 452K
代理商: TLV320AIC24I
SLAS428 AUGUST 2004
www.ti.com
9
LRCK/ADWS
BCLK
DIN
tL(BCLK)
ts(DI)
th(DI)
th(WS)
tS(WS)
tH(BCLK)
tP(BCLK)
Figure 3. I
2
S/LJF/RJF Timing in Slave Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 3)
All specifications at 25
°
C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V
MIN
35
IOVDD = 3.3 V
MIN
35
UNITS
MAX
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
tf
(1)These parameters are based on characterization and are not tested in production.
BCLK high period time
ns
BCLK low period time
35
35
ns
LRCK setup time
6
6
ns
LRCK hold time
6
6
ns
DIN setup time
6
6
ns
DIN hold time
6
6
ns
Rise time
5
4
ns
Fall time
5
4
ns
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