參數(shù)資料
型號(hào)： TLV320AIC27TPFB
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 14/54頁(yè)
文件大小： 732K
代理商： TLV320AIC27TPFB
TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac-link audio output frame (SDATA_OUT) (continued)
SYNC
BIT_CLK
SDATA_OUT
VALID
FRAME
SLOT (1)
SLOT (2)
SYNC ASSERTION HERE
AIC27 SAMPLES
FIRST SDATA_OUT
BIT OF FRAME HERE
END OF PREVIOUS AUDIO FRAME
AIC27 SAMPLES
Figure 10. Start of an Audio Output Frame
A new audio output frame begins with a low-to-high transition of SYNC, as shown in Figure 10. SYNC is
synchronized to the rising edge of BIT_CLK. On the falling edge of BIT_CLK immediately following, the
TLV320AIC27 samples the assertion of SYNC. This falling edge marks the time when both sides of the ac link
are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, AC’97 transitions SDATA_OUT
into the first bit position of slot 0 (valid frame bit). Each new bit position is presented to the ac link on a rising
edge of BIT_CLK, and subsequently sampled by the TLV320AIC27 on the following falling edge of BIT_CLK.
This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data
streams are time-aligned.
Baseline AC’97-specified audio functionality should always convert the sample rate to and from a fixed 48 ksps
on the AC’97 controller. This requirement ensures that interoperability between the AC’97 controller and the
TLV320AIC27, among other things, can be assured by definition for baseline specified AC’97 features.
SDATA_OUT’s composite stream is MSB justified (MSB first), with all invalid slot bit positions stuffed with 0s
by the AC’97 controller. In the event that there are less than 20 valid bits within an assigned and valid time slot,
the AC’97 controller always stuffs all trailing invalid bit positions of the 20-bit slot with 0s.
As an example, consider an eight-bit sample stream that is being played out to one of the TLV320AIC27’s DACs.
The first eight-bit positions are presented to the DAC (MSB justified), followed by the next 12-bit positions, which
are stuffed with 0s by the AC’97 controller. This ensures that, regardless of the resolution of the implemented
DAC (16, 18, or 20-bit), no dc biasing is introduced by the least significant bits. When mono audio sample
streams are outputted from the AC’97 controller, it is necessary that
both left and right sample-stream time slots
be filled with the same data.
slot 1: command address port
The command port is used to control features and monitor status for the TLV320AIC27 functions including, but
not limited to, mixer settings and power management (refer to the serial interface register map). The control
interface architecture supports up to 64 16-bit read/write registers, addressable on even-byte boundaries. Only
the even registers (00h, 02h, etc.) are valid. Access to odd registers (01h, 03h, etc.) is discouraged (if supported,
they should default to the preceding even-byte boundary—that is, a read from 01h returns the 16-bit contents
of 00h). The TLV320AIC27’s control register file is nonetheless readable as well as writeable to provide more
robust testability.
Audio output frame slot 1 communicates control register address and read/write command information to the
TLV320AIC27.
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