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參數(shù)資料
| 型號： | TLV320AIC27TPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 33/54頁 |
| 文件大?。?/td> | 732K |
| 代理商： | TLV320AIC27TPFB |
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TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
quad mode (continued)
The two additional DAC channels are enabled in this mode, using the line level output pins 39 and 41 as outputs.
An additional mixer block in this path allows the analog mix, excluding the front DAC channels, to be summed
into the rear channel mix. Additional gain controls (PGAs) are provided to allow adjustment of front and rear mix
levels separately (registers 72h and 74h) prior to summing the analog mix to these channels. The rear channel
DACs are also gain-adjustable using register 70h. This function duplicates the features provided for the front
DAC channel (gain range, step size, etc.).
quad mode features
D Vendor ID reads back TXN4
D All six audio channels flagged as supported (if I2S enable bit is set)
D Headphone channel flagged as not supported (bit ID4 in register 00h)
D Four channels of DAC and two channels of ADC conversion available, with all recommended audio and
modem sample rates supported via the audio sample-rate registers 2Ch (front channels, slots 3 and 4), 2Eh
(rear channels; slots 7 and 8), and 32h (ADCs). Note that if ID is selected as 11, register 30h is used for
sample rate of LFE channel, slot 9.
D GPIO capability supporting bits 11 to 13 flagged as supported
D Master/slave ID0/1 supported, with automatic remapping of the rear or LFE/center DAC slot data onto the
rear DACs when ID 10 or 11 are selected (normally surround slots are mapped onto the rear DACs).
D LFE and center channel data, plus a duplicate of the rear channel data, is sent from the GPIO pins in I2S
format, at 48 ksps rate (no variable rates supported by the I2S outputs).
D Headphone/line level outputs used to output the rear DAC and mixer channel, with volume controlled from
register 38h.
D 3D stereo enhancement supported
D Master volume control register maps to the location dependant on selected ID: ID 00 or 01 uses master
volume at register 02h, ID 10 uses 38h (surround volume), and ID 11 uses 36h (LFE, center volume). In
ID11 bits 7 and 15 act as left and right mute.
D DAC mute (reg18h) automatically demuted when ID is 1x, that is, used as surround DAC or LFE/center
when surround or LFE/center master volume is demuted.
D In order to achieve the above functionality, the following changes to the Revision 2.1 compliant defaults are
required:
Revision 2.1 legacy compliance switch is opened (can be closed using REV2SW bit in register 5Ah)
Rear channel mixer PGA default is now not muted, 0-dB gain (same as front channel mixer)
LNLVL pin volume control is now controlled from 02h, unless ID = IO when volume control is from 38h
Rear DAC level set by register 70h, default is 0-dB not-muted
Front mixer and rear mixer gains set in registers 72h and 74h
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| TLV320AIC28 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
| TLV320AIC28_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO CODEC WITH INTEGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
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| TLV320AIC28IRGZG4 | 功能描述:接口—CODEC Lo-Pwr Stereo Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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