TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register 4Eh – GPIO pin polarity/type
The GPIO pin polarity/type is a read/write register that defines the GPIO input polarity (0 = low, 1 = high active)
when a GPIO pin is configured as an input. It defines GPIO output type (1 = CMOS, 0 = open drain) when a GPIO
pin is configured as an output.
The default value of this register (FFFFh) after cold or register reset is all pins active high. Nonimplemented
GPIO pins always return 1s.
register 50h – GPIO pin sticky control
The GPIO pin sticky control is a read/write register that defines GPIO input type (0 = nonsticky, 1 = sticky) when
a GPIO pin is configured as an input. GPIO inputs configured as sticky are cleared by writing a 0 to the
corresponding bit of the GPIO pin status register 54h (see below), or by resetting it.
The default value of this register (0000h) after a cold or register reset. Unimplemented GPIO pins always return
0s. Sticky is defined as edge-sensitive, nonsticky is defined as level-sensitive.
register 52h – GPIO pin wake-up control
The GPIO wake-up pin is a read/write register that provides a mask for determining if an input GPIO change
will generate a wake up or a GPIO_INT (0 = no, 1 = yes). When the ac link is powered down (register 26h
PR4 = 1 for primary codecs), a wake-up event triggers the assertion of SDATA_IN. When the ac link is powered
up, a wake-up event will appear as GPIO_INT = 1 on bit 0 of input slot 12. GPIO_INT is also flagged when the
link is active.
An ac-link wake-up interrupt is defined as a 0 to 1 transition of SDATA_IN when the ac link is powered down
(register 26h PR4 = 1). The GPIO bits that have been programmed as inputs (sticky and wake-up) will cause
an ac-link wake-up event (transition of SDATA_IN from 0 to 1) upon either (high-to-low) or (low-to-high) transition
(depending on pin polarity) only if the ac link was powered down.
The default value of this register (0000h) after a cold or register reset is all 0s, specifying no wake-up event.
Nonimplemented GPIO pins always return 0s.
register 54h – GPIO pin status
The GPIO status is a read/write register that reflects the state of all GPIO pins (inputs and outputs) on slot 12.
The value of all GPIO pin inputs and outputs comes in from the codec on slot 12 at every frame. This value is
also available for reading as GPIO pin status via the standard slots 1 and 2 command address/data protocols.
GPIO inputs configured as sticky are cleared by writing a 0 to the corresponding bit of register 54h.
Bits corresponding to unimplemented GPIO pins should be forced to zero in this register and input slot 12. GPIO
bits that have been programmed as inputs and sticky, upon either (high-to-low) or (low-to-high) transition,
depending on pin polarity, will cause the individual GPIO bit to be asserted to 1 and remain asserted until a write
of 0 to that bit. The normal way to set the desired value of a GPIO output pin is to set the control bit in output
slot 12.
If configured as an input, the default value of this register after a cold or register reset is always the state of the
GPIO pin.
register 56h – miscellaneous modem AFE status/control
Not supported in this mode.
vendor reserved registers (index 5Ah and 7Ah)
These registers are vendor-specific. Do not write to these registers unless the vendor ID register has been
checked first to ensure that the driver knows the source of the AC‘97 component. Values stored in this register
are used to provide vendor-specific modes for the manufacturer.