參數(shù)資料
型號： TLV320AIC3111IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 144/156頁
文件大小： 1701K
代理商： TLV320AIC3111IRHBT
SLAS644B – JULY 2009 – REVISED OCTOBER 2009
www.ti.com
Page 0 / Register 37: DAC Flag Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
0: Left-channel DAC powered down
1: Left-channel DAC powered up
D6
R/W
X
Reserved. Write only zero to this bit.
D5
R
0
0: HPl driver powered down
1: HPL driver powered up
D4
R
0
0: Left-channel class-D driver powered down
1: Left-channel class-D driver powered up
D3
R
0
0: Right-channel DAC powered down
1: Right-channel DAC powered up
D2
R/W
X
Reserved. Write only zero to this bit.
D1
R
0
0: HPR driver powered down
1: HPR driver powered up
D0
R
0
0: Right-channel class-D driver powered down
1: Right-channel class-D driver powered up
Page 0 / Register 38: DAC Flag Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
XXX
Reserved. Do not write to these bits.
D4
R
0
0: Left-channel DAC PGA applied gain
≠ programmed gain
1: Left-channel DAC PGA applied gain = programmed gain
D3–D1
R/W
XXX
Reserved. Write only zeros to these bits.
D0
R
0
0: Right-channel DAC PGA applied gain
≠ programmed gain
1: Right-channel DAC PGA applied gain = programmed gain
Page 0 / Register 39: Overflow Flags
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7(1)
R
0
Left-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D6(1)
R
0
Right-Channel DAC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D5(1)
R
0
DAC Barrel Shifter Output Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D4
R/W
0
Reserved. Write only zeros to these bits.
D3(1)
R
0
Delta-Sigma Mono ADC Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D2
R/W
0
Reserved. Write only zero to this bit.
D1(1)
R
0
ADC Barrel Shifter Output Overflow Flag
0: Overflow has not occurred.
1: Overflow has occurred.
D0
R/W
0
Reserved. Write only zero to this bit.
(1)
Sticky flag bIts. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Register 40 Through Page 0 / Register 43: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Write only the reset value to these bits.
88
REGISTER MAP
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3111
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