參數(shù)資料
型號(hào): TLV320AIC3120IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 1/150頁
文件大?。?/td> 1507K
代理商: TLV320AIC3120IRHBR
www.ti.com
SLAS653 – FEBRUARY 2010
Low-Power Mono Audio Codec With Embedded miniDSP
and Mono Class-D Speaker Amplifier
Check for Samples: TLV320AIC3120
1
INTRODUCTION
1.1
Features
1.2
Applications
123
Mono Audio DAC With 95-dB SNR
Portable Audio Devices
Mono Audio ADC With 90-dB SNR
Mobile Internet Devices
Supports 8-kHz to 192-kHz Separate DAC and
ADC Sample Rates
eBooks
Instruction-Programmable Embedded miniDSP
Adaptive Filtering Applications
Mono Class-D BTL Speaker Driver (2.5 W Into
4
or 1.6 W Into 8 ) Output
1.3
Description
Mono Headphone/Lineout Outputs
The TLV320AIC3120 is a low-power, highly
One Differential or Three Single-Ended Inputs
integrated,
high-performance
codec
which
With Mixing and Level Control
features a mono audio DAC and mono audio
Microphone With Bias, Preamp PGA, and AGC
ADC.
Built-in Digital Audio Processing Blocks (PRB)
With User-Programmable Biquad, FIR Filters,
The
TLV320AIC3120
features
a
and DRC
high-performance
audio
codec
with
24-bit
Bass Boost/Treble/EQ With up to Five Biquads
mono playback and mono record functionality.
for Record and up to Six Biquads for Playback
The device integrates several analog features,
Digital Mixing Capability
such as a microphone interface, headphone
Pin Control or Register Control for Digital
drivers,
and
speaker
drivers.
The
Playback Volume Control Settings
TLV320AIC3120 has a fully programmable
Programmble PLL for Flexible Clock
miniDSP for digital audio processing. The
Generation
digital audio data format is programmable to
I2S, Left-Justified, Right-Justified, DSP, and
work with popular audio standard protocols
TDM Audio Interfaces
(I2S, left/right-justified) in master, slave, DSP,
I2C Control With Register Auto-Increment
and TDM modes. Bass boost, treble, or EQ
Full Power-Down Control
can be supported by the programmable digital
Power Supplies:
signal-processing blocks (PRB). An on-chip
– Analog: 2.7 V–3.6 V
PLL provides the high-speed clock needed by
– Digital Core: 1.65 V–1.95 V
the digital signal-processing block. The volume
– Digital I/O: 1.1 V–3.6 V
level can be controlled either by pin control or
– Class-D: 2.7 V–5.5V (SPKVDD
≥ AVDD)
by register control. The audio functions are
controlled using the I2C serial bus.
5-mm × 5-mm 32-QFN Package
The TLV320AIC3120 is available in a 32-pin
QFN package. PurePath Studio
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PurePath Studio is a trademark of Texas Instruments.
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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