參數(shù)資料
型號(hào): TLV571IPWR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝: GREEN, PLASTIC, TSSOP-24
文件頁(yè)數(shù): 2/28頁(yè)
文件大?。?/td> 479K
代理商: TLV571IPWR
TL
V571
2.7
V
to
5.5
V
,1-CHANNEL,
8-BIT
RARALLEL
ANALOG-T
O-DIGIT
AL
CONVERTER
SLAS239A
SEPTEMBER
1999
REVISED
FEBRUAR
Y
2000
10
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
software START conversion
external clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks
after sampling begins. At the end of conversion, the INT goes low telling the host that conversion is ready to be read out. EOC B low during
the conversion. The external clock is active and used as the reference at all times. With this mode, WR and RD should not be applied at the
rising edge of the clock (see Figure 3).
Auto Powerdown
CLK
CS
WR
RD
D[0:7]
INT
EOC
Config
Data
ADC Data
t su(CSL_WRL)
th(WRH_CSH)
t su(DAV_WRH)
t h(WRH_DAV)
tc
t su(CSL_RDL)
t
h(RDH_CSH)
t en(RDL_DAV)
t dis(RDH_DAV)
tc
t
t en(RDL_DAV)
01
5
6
7
15
16
OR
su(CSL_RDL)
t(sample)
04
5
15
Figure 6. Input Conversion – Software Start, External Clock
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