參數(shù)資料
型號(hào)： TLV571IPWR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝： GREEN, PLASTIC, TSSOP-24
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 479K
代理商： TLV571IPWR
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simplified analog input analysis
Using the equivalent circuit in Figure 10, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB, tch(1/2 LSB), can be derived as follows.
The capacitance charging voltage is given by:
Where
Rt = Rs + Ri
Ri = Ri(ADC)
tch = Charge time
V
C(t) +
V
S
1–e
–t
ch
RtCi
The input impedance Ri is 718 at 5 V, and is higher (~ 1.25 k) at 2.7 V. The final voltage to 1/2 LSB is given
by:
VC (1/2 LSB) = VS – (VS/512)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1/2 LSB) = Rt × Ci × ln(512)
V
S *
V
S
512
+ V
S
1–e
–t
ch
RtCi
Where
ln(512) = 6.238
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 LSB) = (Rs + 718 ) × 15 pF × ln(512)
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.
tch (1/2 LSB) ≤ 6x 1/f(SCLK)
Therefore the maximum SCLK frequency is:
Max(f(SCLK)) = 6/tch (1/2 LSB) = 6/(ln(512) × Rt × Ci)
(1)
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