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參數(shù)資料
| 型號： | TMC2301 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器) |
| 中文描述： | 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器） |
| 文件頁數(shù)： | 16/26頁 |
| 文件大小： | 237K |
| 代理商： | TMC2301 |
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TMC2301
PRODUCT SPECIFICATION
16
6.
The procedure continues until (UMAX + 1, VMIN) is
reached, at which point the device resets to U (position
within row) and increments V (number of row). Thus,
the next (U, V) set after (UMAX + 1, VMIN) will be
(UMIN, VMIN + 1), followed by (UMIN + 1,
VMIN + 1), etc.
7.
Upon completion of the walk corresponding to
(UMAX + 1, VMAX + 1), the TMC2301 will generate a
DONE flag with the final UWRI, and begin a new
sequence.
On any given clock cycle, the actual (X, Y) and (U, V) out-
puts of the IRS are given by the following equations:
x = X
0
+ dX/dU
0
* m + dX/dV
0
* n + d
2
X/dUdV * m * n
+ d
2
X/dU
2
* (m2 – m)/2 + d
2
X/dV
2
* (n
2
– n)/2
+ FOV * CAX(w) + FOV * m * CAX(Ker)
y = Y
0
+ dY/dU
0
* m + dX/dV
0
* n + d
2
Y/dUdV * m * n
+ d
2
Y/dU
2
* (m2 – m)/2 + d
2
Y/dV
2
* (n
2
– n)/2
+ FOV * CAY(w) + FOV * m * CAY(Ker)
u = UMIN + m
v = VMIN + n
where FOV is the 4-bit field of view parameter, normally set
to 1 so that the spiral walk proceeds in single-pixel steps.
Setting FOV to 4 would expand the spiral walk, allowing the
user to trade two bits of image size for two bits of additional
interpixel positioning resolution. CAX(w) and CAY(w) are
the current value of the coefficient address outputs and
CAX(KER) and CAY(KER) are the terminal values of each
pixel walk. The CA(KER) terms arise because the IRS com-
putes each new walk's starting paint from the previous spiral
walk's end point rather than its starting point.
Interpolation Coefficient Lookup Table
Addressing
The external coefficient lookup table RAM stores the inter-
polation values used to calculate the value of the new pixel.
These values are selected by the user allowing maximum fil-
tering flexibility. In simple filtering applications, all 8 bits of
coefficient address are available to access up to 256 interpo-
lation coefficients, for kernels of 16 x 16 pixels. This address
is generated by the internal walk counter of the TMC2301. In
most applications, the same Kernel parameter value is
selected in both IRS devices; thus, the Coefficient Address
outputs CA
7-0
for the X and Y devices are identical, and the
user needs only one of the 8-bit buses for memory access.
Applications executing a coordinate transformation, however
will almost always generate non-integer source pixel
addresses; that is the U (or V) locations will not map to the X
(or Y) addresses exactly and fractional address components
are generated. The user then must account for this spatial off-
set in both dimensions by storing the appropriate corrected
interpolation kernel values in the lookup table. The 8-bit
address bus is broken up into two parts: the fractional portion
(upper 4 bits), and the walk counter (lower 4 bits). Thus, in
resampling applications, the maximum kernel size is 4 x 4
pixels, or 16 locations. As in the filtering example, assuming
that the user has selected the same kernel size for both IRS
devices, the 4 bits of least-significant address generated by
both devices will be identical and redundant. The four most
significant address bits, however, will reflect the current frac-
tional offsets of the resampled pixel from the nearest X (Y)
location, to a spatial resolution of 4 bits in the X (or Y) direc-
tions. Utilization of the 12 bits (total) of lookup table address
is left to the user to be arranged as desired for memory
access. See Figure 3.
Application Examples
One of the more common applications for the TMC2301 is
simple static filtering In this case the source and target mem-
ories locations are identical and no coordinate transforma-
tion is performed. The (X, Y) and (U, V) outputs listed in
Table 4 show the address sequencing generated by the
TMC2301 to execute the walk of a 5 x 5 pixel interpolation
kernel. The normalized coefficients shown implement a first-
order Butterworth Low Pass Filter with cutoff radius of
1/
. Note that the (U, V) output address is updated follow-
ing the completion of the walk for that location.
Figure 9. Pixel Map Showing Walk Sequence
for 5x5 Static Filter
2
(0, 0)
65-2301-14
20
21
22
23
24
7
8
0
1
9
15
14
13
4
3
2
12
19
18
17
10
11
6
5
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2302A | Image Manipulation Sequencer |
| TMC2302AH5C | Image Manipulation Sequencer |
| TMC2302AH5C1 | Image Manipulation Sequencer |
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
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