參數(shù)資料
型號： TMC2301
廠商： Fairchild Semiconductor Corporation
英文描述： 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器)
中文描述： 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器）
文件頁數(shù)： 5/26頁
文件大小： 237K
代理商： TMC2301
PRODUCT SPECIFICATION
TMC2301
5
Pin Descriptions
Pin Name
Power
GND
Pin Number
PGA
Pin Function Description
PLCC
F2, F10, K1,
K6, L10, B6
L5, A6
1, 9, 18, 35,
52, 60
36, 68
Supply Voltage.
The TMC2301 operates from a single +5V
supply. All pins must be connected.
Ground.
The TMC2301 operates from a single +5V supply. All
pins must be connected.
V
DD
Clock
CLK
A7
34
System Clock.
The TMC2301 has a angle clock input. The rising
edge of CLK strobes all enabled registers. All timing
specifications are referenced to the rising edge of CLK.
Inputs
B
3-0
A3, B3, A4, B4
42-39
Parameter Register Address.
The write addresses for the
individual coordinate transform parameters are presented at the
registered 4-bit B input port. B
3
is the Most Significant Bit.
Parameter Register Data.
The coordinate transformation
parameters are loaded through the registered 12-bit P input port.
P11 is the Most Significant Bit.
P
11-0
D10, D11,
C10, C11,
B11, B10, A10,
B9, A9, B8,
A8, B7
22-33
Outputs
CA
7-0
K9, L8, K8, L7,
K7, L6, K5, L4
7-2, 67, 66
Coefficient Address.
The current interpolation kernel coefficient
lookup table address is indicated by the registered 8-bit CA
7-0
output bus. This output is forced to the high impedance state
when NOOP is LOW. CA
7
is the Most Significant Bit.
Target Address.
The U (or V) target address of the image being
generated is indicated by the registered 12-bit U
11-0
output bus.
This output is forced to the high impedance state when OETA is
HIGH. U
11
is the Most Significant Bit.
Source Address.
The current X (or Y) source pixel address of
the image being resampled is indicated by the registered 12-bit
X
11-0
output bus. This output is forced to the high impedance
state when NOOP is LOW. X
11
is the Most Significant Bit.
U
11-0
L2, K2, J1, J2,
H1, H2, G1,
G2, F1, E1,
E2, D1
E11, E10, F11,
G11, G10,
H11, H10, J11,
J10, K11, K10,
L9
62, 61, 59-53,
51-49
X
11-0
21-19, 17-10,
8
Controls
ACC
L3
64
Accumulate.
The accumulation register of the external multiplier-
accumulator is initialized by the registered ACC output. ACC
goes LOW for one cycle at the start of each interpolation "walk,"
effectively clearing the storage register by loading in only the new
first product. See Figure 9.
Initialize.
The control logic is cleared and initialized for the start
of a new image transformation when the registered INIT input is
HIGH for a minimum of two clock cycles. Normal operation begins
after INIT goes LOW.
Interconnect.
In the common two-device system configuration,
the Interconnect inputs are connected to the END flag outputs.
The END flag from the row (X) sequencer thus indicates an "end
of line" to the column (Y) device, while the column sequencer in
turn sends a "bottom of frame" signal to the row device, forcing a
reset of the address counter.
INIT
B2
44
INTER
C2
46
相關(guān)PDF資料
PDF描述
TMC2302A Image Manipulation Sequencer
TMC2302AH5C Image Manipulation Sequencer
TMC2302AH5C1 Image Manipulation Sequencer
TMC2302AKEC Image Manipulation Sequencer
TMC2302AKEC1 Image Manipulation Sequencer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMC2302A 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2302AH5C 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC2302AH5C1 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC2302AKEC 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2302AKEC1 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
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