參數(shù)資料
型號(hào)： TMC2301
廠商： Fairchild Semiconductor Corporation
英文描述： 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器)
中文描述： 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器）
文件頁(yè)數(shù)： 8/26頁(yè)
文件大?。?/td> 237K
代理商： TMC2301
TMC2301
PRODUCT SPECIFICATION
8
In single-pass operation, the device walks through the entire
(k + 1) x (k + 1) kernel for each output pixel, where k is the
value written into the Kernel section (see below) of the
parameter register. Two-pass operation, which requires a
dimensionally separable kernel, is executed first for a (k + 1)
element kernel in one direction, then for a (k + 1) element
kernel in the other direction. For kernel sizes exceeding
2 x 2, the two-pass algorithm is obviously beneficial, requir-
ing 2n samples per output point instead of n x n. In this case,
the intermediate image data stored in the destination image
memory following the first pass is used as the source image
data on the second pass. The user may design a system to
d
2
Y/dU
2
Is the second order vertical-
horizontal-horizontal derivative. It
indicates the rate of change of the
the vertical-horizontal first derivative
with each step along a line of the
output image space.
Is the second order vertical
derivative. It indicates the rate of
change of the vertical-vertical first
derivative with each step down a
column of the output image space.
Is the mixed second order derivative
indicating the rate of change of the
first order horizontal derivative as
one proceeds downwards through
the output image space. This is also
the rate of change of the first order
horizontal-vertical derivative during
horizontal sweeps in the output
image space.
Is the mixed second order derivative
indicating the rate of change of the
first order vertical derivative as one
moves horizontally across the output
space, or, equivalently, the rate of
change of the first order vertical-
horizontal derivative as one moves
vertically in the output image space
Sets the mode to either Row (0) or
Column (1) operation.
This 2-bit control word defines three
unique instructions:
d
2
Y/dV
2
d
2
X/dUdV
d
2
Y/dUdV
Row/Column
Select
Mode
Code
00, 01
10
Instruction
single-pass operation
pass 1 of two-pass
operation
pass 2 of two pass
operation
11
switch source and destination memory bank addresses in
place, or could utilize a second TMC2301 pair in a pipelined
architecture. This would require a third image buffer for the
final destination image. Both devices of a system pair are
usually set to the same mode.
Kernel
The effective kernel width (height)
exceeds this 4-bit unsigned number by 1,
thereby providing kernels of 1 x 1 to
16 x 16 source pixels per output, for
either resampling or filtering. Simple
static filters can be implemented with
kernels of up to 16 x 16 pixels (Kernel =
15), while resampling interpolation
kernels are limited to 4 x 4 pixels (Kernel
= 3), due to the four bits of fractional X (or
Y) address generated by the TMC2301.
See the Applications Discussion. Again,
both devices in a pair are generally
initialized with equal Kernel values.
As the device walks through its kernel
coefficients, each corresponding step in
(x, y) space is normally one pixel length
or height; this is a field of view of 1.
However, the user can subsample the
original space before filtering or
resampling, by applying the coefficient
kernel over a view field of up to 7 units. At
a field of view of F, the pixels selected for
each kernel operation are F pixels apart.
This is useful in oversampled pictures,
whose intensity changes only slowly from
pixel to pixel.
When set to 1 (HIGH), the LDR control is
automatically asserted when INIT is
strobed, loading the coefficient set
currently stored in the preload registers.
At the end of an image, if the AIN bit is 1
(HIGH) the DONE flag goes HIGH for
one clock cycle and a new transform
begins. If 0 (LOW), UWRI and the DONE
flag remain HIGH during the sequence
until the user strobes the INIT control to
begin a new image transformation.
Adjusts the timing of the target memory
write controls, to compensate for
buffered source image RAM. If the PIPE
bit is 1 (HIGH), outputs ACC and UWRI
will be delayed one clock cycle relative to
the generation of the target address (U or
V). See Figure 9.
Field of
View
(FOV)
Autoload
(ALR)
Autoinit
(AIN)
Pipe
(PIPE)
相關(guān)PDF資料
PDF描述
TMC2302A Image Manipulation Sequencer
TMC2302AH5C Image Manipulation Sequencer
TMC2302AH5C1 Image Manipulation Sequencer
TMC2302AKEC Image Manipulation Sequencer
TMC2302AKEC1 Image Manipulation Sequencer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMC2302A 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2302AH5C 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC2302AH5C1 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC2302AKEC 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2302AKEC1 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
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