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參數(shù)資料
| 型號： | TMC2302A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 圖像處理序列 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302A |
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TMC2302A
PRODUCT SPECIFICATION
10
P
TVAL
M13
63
Target Address Valid.
are within the working space defined by the parameters UMINI and
UMAXI, and VMINI and VMAXI (and WMINI and WMAXI for
systems processing three-dimensional images), the Target
Address Valid flag TVAL for that device is LOW. This flag will go
HIGH on the clock in which the current target address outputs fall
outside the defined region, which must fall inside the target area
defined by UMIN, UMAX, etc. Since each TMC2302A device is
programmed with distinct MINI/MAXI parameters and generates a
separate TVAL flag, the user may define separate two or three-
dimensional target space windows for each device. TVAL can be
delayed up to seven clock cycles after the nominal sequence
shown in Table 4 by the pipeline delay parameter PIPTVA. See the
Device Configuration and Control Parameters section.
End of Dimension.
During the last pixel interpolation walk of a row
(X/U device), the last row in a page (Y/V device), or the last page in
a three-dimensional transform (Z/W device), the flag ENDD goes
HIGH for the entire walk, indicating End of the transform in that
dimension. It remains LOW otherwise. This output can be delayed
up to seven clock cycles after the nominal sequence shown in
Table 4 by the pipeline delay parameter PIPEND. See the Device
Configuration and Control Parameters section.
Done.
On the last clock cycle of the current image transform, the
DONE flags on all TMC2302As go HIGH for one clock cycle. On
the next clock cycle, all devices output the first addresses and
control signals for the next image transform. If SYNC is LOW, the
IMS system halts. If SYNC is HIGH, operation continues without
interruption. See “SYNC,” in the Controls section. This flag can be
delayed up to seven clock cycles after the nominal sequence
shown in Table 4 by the pipeline delay parameter PIPDON. Also
see “PFLS,” in the Device Configuration and Control Parameters
section.
When the current target image addresses
ENDD
N13
60
DONE
L10
57
No Connects
NC
L3
D4
59
—
No Connect.
Index Pin.
Pin Descriptions
(continued)
Pin Name
Pin Number
PPGA
Pin Function Description
MQFP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2302AH5C | Image Manipulation Sequencer |
| TMC2302AH5C1 | Image Manipulation Sequencer |
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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