參數(shù)資料
型號(hào)： TMC2302A
廠商： Fairchild Semiconductor Corporation
英文描述： Image Manipulation Sequencer
中文描述： 圖像處理序列
文件頁(yè)數(shù)： 8/36頁(yè)
文件大小： 188K
代理商： TMC2302A
TMC2302A
PRODUCT SPECIFICATION
8
P
TADR
11-0
N12, N11,
M10, L9,
N10, M9,
N9, L8, M8,
N8, N7, M7
56, 55, 54,
53, 52, 51,
50, 49, 48,
47, 46, 44
Target Address.
the target image pixel value just resampled is output through the
Target Address Port TADR
11-0
. This port is forced into the high-
impedance state by the enable control OET. TADR
delayed up to seven clock cycles after the nominal sequence
shown in Table 4 by utilization of the pipeline delay parameter
PIPTAD. For systems requiring greater spatial resolution in the
source image than that offered by the SADR
Address Port can be reconfigured to output 12 additional LSBs of
the source address by placing the device into the Extended mode,
in which case the pipeline delay parameter must be set to 0 to
maintain alignment with the current source address port output.
See the Device Configuration and Control Parameters section.
The 12-bit address of one dimension (U, V, W) of
11-0
can be
23-0
alone, the Target
Controls
INIT
K12
67
Initialize.
the start of a new image transformation, and the internal working
registers are updated with the contents of the current control
parameter preload registers when the registered control input INIT
is HIGH. The image transformation then commences with the first
source image pixel address nine clocks after INIT is returned low.
Run/Halt.
The user can select between continuous or one-frame
operation with the registered input control SYNC. Assuming that
INIT remains LOW and NOOP remains HIGH, if SYNC remains
HIGH at the end of a transform the TMC2302A will begin the next
image transformation without interruption. This assumes either that
the user is not changing the parameter set, or that a new set of
parameters has already been loaded into the preload registers
midframe, prior to the beginning of the last line in the transform. If
SYNC is LOW during the last clock cycle of a transform, the device
will complete the image, having loaded the new transform
parameter set during the first clock of the final line of the transform,
and halt in the state set on the first clock cycle of the next
transform. These outputs are held until SYNC is again brought
HIGH, and operation resumes on the next clock. See Figure 5.
Input Parameter Chip Select.
The input parameter preload
register write clock IWR, and thus the preloading of all
configuration and transformation parameters, is disabled on the
next clock when the registered Input parameter Chip Select input is
HIGH. When ICS returns LOW, they are enabled on the next clock.
See Figure 3
.
Accumulate.
The external pixel interpolator or multiplier-
accumulator is initialized for a new accumulation of products by the
registered Accumulator Control output ACC. On the first cycle of
each interpolation walk, this output goes LOW for one cycle,
effectively clearing the register by loading in only the first new
resampled pixel value. When performing nearest-neighbor
resampling, this control will remain LOW throughout the entire
transform. This output can be delayed up to seven clock cycles
after the nominal sequence shown in Table 4 by the pipeline delay
parameter PIPACC. See the Device Configuration and Control
Parameters section.
The TMC2302A control logic is cleared and initialized for
SYNC
H13
74
ICS
B9
100
ACC
M1
27
Pin Descriptions
(continued)
Pin Name
Pin Number
PPGA
Pin Function Description
MQFP
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