參數(shù)資料
型號(hào)： TMP320F2810PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 41/103頁(yè)
文件大?。?/td> 1341K
代理商： TMP320F2810PBKS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
PIE/CPU interrupt response
Figure 8 shows the behavior of the PIE hardware under various PIEIFR and PIEIER register conditions. There
is one PIEACK bit for every CPU interrupt group (INT1 to INT12) and is referred to as PIEACK(x). There is a
corresponding PIEIFR and PIEIER register for each group and are referred to as the PIEIFRx and PIEIERx
registers. Figure 8 describes the operation of one PIE interrupt. This flow is common to all PIE interrupts.
Start
Stage A
PIEIFRx.y = 1
Stage B
PIEIERx.y = 1
Stage C
PIEACKx = 0
Yes
Yes
Yes
Wait for S/W
to Clear
PIEACKx Bit = 0
Wait for PIEIERx.y = 1
Wait for any
PIEIFRx.y = 1
Stage D
Interrupt Request Sent to
28x CPU on INTx
Stage E
IFRx Bit Set 1
Interrupts to
CPU
Stage F
IERx Bit = 1
Stage G
INTM Bit = 0
Stage H
CPU Responds
Branches to Vector Address at PIEIFRx.y
IFRx Bit Cleared
Context Save
IER = 0
INTM = 1
PIEIFRx.y Bit Cleared
Stage I
Interrupt Service Routine Responds
Write 1 to PIEACKx Bit to Clear to Enable
Other Interrupts in PIEIFRx Group
Re-enable Interrupts, INTM = 0
Return
Yes
Yes
No
Wait for
IERx = 1
Wait for INTM = 0
End
Vector Branch
Interrupt Service
Routine (ISR)
for PIEIFRx.y
PIE Interrupt
Control
CPU Interrupt
Control
No
No
No
No
Figure 8. Typical PIE/CPU Interrupt Response
–
INTx.y
P
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