參數(shù)資料
型號(hào)： TMP320F2810PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 80/103頁(yè)
文件大?。?/td> 1341K
代理商： TMP320F2810PBKS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
80
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
serial communications interface (SCI) module (continued)
The SCI port operation is configured and controlled by the registers listed in Table 57 and Table 58.
Table 57. SCI-A Registers
NAME
ADDRESS RANGE
SIZE (x16)
DESCRIPTION
SCICCR
0x0000
–
7050
1
SCI-A Communications Control Register
SCICTL1
0x0000
–
7051
1
SCI-A Control Register 1
SCIHBAUD
0x0000
–
7052
1
SCI-A Baud Register, High Bits
SCILBAUD
0x0000
–
7053
1
SCI-A Baud Register, Low Bits
SCICTL2
0x0000
–
7054
1
SCI-A Control Register 2
SCIRXST
0x0000
–
7055
1
SCI-A Receive Status Register
SCIRXEMU
0x0000
–
7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUF
0x0000
–
7057
1
SCI-A Receive Data Buffer Register
SCITXBUF
0x0000
–
7059
1
SCI-A Transmit Data Buffer Register
SCIFFTX
0x0000
–
705A
1
SCI-A FIFO Transmit Register
SCIFFRX
0x0000
–
705B
1
SCI-A FIFO Receive Register
SCIFFCT
0x0000
–
705C
1
SCI-A FIFO Control Register
SCIPRI
0x0000
–
705F
1
SCI-A Priority Control Register
Shaded registers are new registers for the FIFO mode.
Table 58. SCI-B Registers
NAME
ADDRESS RANGE
SIZE (x16)
DESCRIPTION
SCICCR
0x0000
–
7750
1
SCI-B Communications Control Register
SCICTL1
0x0000
–
7751
1
SCI-B Control Register 1
SCIHBAUD
0x0000
–
7752
1
SCI-B Baud Register, High Bits
SCILBAUD
0x0000
–
7753
1
SCI-B Baud Register, Low Bits
SCICTL2
0x0000
–
7754
1
SCI-B Control Register 2
SCIRXST
0x0000
–
7755
1
SCI-B Receive Status Register
SCIRXEMU
0x0000
–
7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUF
0x0000
–
7757
1
SCI-B Receive Data Buffer Register
SCITXBUF
0x0000
–
7759
1
SCI-B Transmit Data Buffer Register
SCIFFTX
0x0000
–
775A
1
SCI-B FIFO Transmit Register
SCIFFRX
0x0000
–
775B
1
SCI-B FIFO Receive Register
SCIFFCT
0x0000
–
775C
1
SCI-B FIFO Control Register
SCIPRI
0x0000
–
775F
1
SCI-B Priority Control Register
Shaded registers are new registers for the FIFO mode.
Note:
The above registers are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit
accesses produce undefined results.
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