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參數(shù)資料
| 型號： | TMP320F2810PGFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 19/103頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | TMP320F2810PGFA |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
peripheral interrupt expansion (PIE) block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the F2810/F2812, 45 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into one of 12 CPU interrupt
lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block
that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.
It takes 9 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly
respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual
interrupt can be enabled/disabled within the PIE block.
external interrupts (XINT1, 2, 13, XNMI)
The F2810 and F2812 support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one
non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can
be selected for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The
masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge
is detected. This counter can be used to accurately time stamp the interrupt.
oscillator and PLL
The F2810 and F2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator
circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed
on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is
desired. The PLL block can be set in bypass mode.
watchdog
The F2810 and F2812 support a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can
be disabled if necessary.
peripheral clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports and the event managers, CAP and QEP
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from
increasing CPU clock speeds.
low-power modes
The F2810 and F2812 devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins on
the next valid cycle after detection of the interrupt event.
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. Only a reset or XNMI will wake the device from this mode.
STANDBY:
HALT:
P
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