參數(shù)資料
型號(hào): TMP320F2810PGFA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: DIGITAL SIGNAL PROCESSORS
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 87/103頁(yè)
文件大小: 1341K
代理商: TMP320F2810PGFA
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
APRIL 2001
REVISED SEPTEMBER 2001
87
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
GPIO mux (continued)
Figure 21 shows how the various register bits select the various modes of operation.
Peripheral I/O
MUX
0
1
MUX
1
0
PIN
Internal (Pullup or Pulldown)
HSPCLK (High-Speed Peripheral Clock)
Digital I/O
QUALxCLK
Boundary Off
XRS
High-Impedance
Enable (1)
High-
Impedance
Control
GPxDIR
Register Bit
GPxMUX
Register Bit
GPxQUAL
Register
GPxDAT/SET/CLEAR/TOGGLE
Register Bit(s)
Input
Qualification
Pre-Scale
Figure 21. Modes of Operation
Notes:
1.
Via the GPxDAT register, the state of any PIN can be read, regardless of the operating mode.
2.
Some selected input signals are, qualified by the QUALxCLK, which is a prescaled version of the
high-speed peripheral clock (HSPCLK). The GPxQUAL register specifies the qualification sampling period.
The sampling window is 6 samples wide and the output is only changed when all samples are the same
(all 0
s or all 1
s) as shown in Figure 22. This feature removes unwanted spikes from the input signal.
P
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