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參數(shù)資料
| 型號(hào)： | TMP90CM36 |
| 廠商： | Toshiba Corporation |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | High Speed Advanced CMOS 8-bit Microcontroller,Integrating RAM，ROM，General Serial Interface,Multifuction Timer/Event Counter，Signal Selector Circuit,PWM Output(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了ROM，RAM，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器,信號(hào)選擇電路，PWM輸出）) |
| 中文描述： | 采用先進(jìn)的CMOS高速8位微控制器，集成內(nèi)存，光盤(pán)，通用串行接口，Multifuction定時(shí)器/事件計(jì)數(shù)器，信號(hào)選擇器電路，PWM輸出（高速，先進(jìn)的的CMOS 8位微控制器（芯片集成了ROM和RAM內(nèi)存，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器，信號(hào)選擇電路，脈寬調(diào)制輸出）） |
| 文件頁(yè)數(shù)： | 134/194頁(yè) |
| 文件大?。?/td> | 7013K |
| 代理商： | TMP90CM36 |
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134
TOSHIBA CORPORATION
TMP90CM36
(2)
Receive Mode
Setting the command register to receive mode, then
setting serial serial transfer control SCMOD2 <SIOE>
to enable makes receive possible. Shift data is syn-
chronized with serial clock pulses and fetched from
the RxD2 pin. When data is fetched, it is transferred
from the shift register to the buffer register and the
buffer-full interrupt INTRX2 is generated to request a
read of receive data.
When the interrupt service program read the next
receive data from the buffer register, the interrupt
request signal is cleared. The following data continues
to be fetched after the interrupt is generated.
After the interrupt request is cleared, data is trans-
ferred from the shift register to the buffer register when
data is fetched.
(Internal clock pulses)
In the internal clock operation, if the previous receive
data has not been read from the buffer regfister after
the next data is fetched, the serial clock stops and
waits until the previous data is read.
(External clock pulses)
In the external operation, shift operations are synchro-
nized with externally supplied clock pulses. The data is
read before the next receive data is transferred into the
buffer register. If the previous data has not been read,
the receive data will not be transferred into the buffer
registers and all subsequently input receive data will
be cancelled. The maximum transfer speed of the
external clock operation is determined by the maxi-
mum delay time from interrupt request generation to
receive data read.
Rising and falling edge shifts can be selected in the
receive mode. Because data is fetched on the serial
clock pulses’s rising edge in the rising edge shift, the
first shift data must already be input to the RxD2 pin
when the initial serial clock pulses are applied at trans-
fer start.
(3)
Send-Receive Mode
The first send data is written into buffer registers
SCBUF2 after the send-receive mode is set by the
command register. Setting the serial transfer control
register SCMOD2 <SIOE> to 1 enables receiving or
sending data. Send data is output from the TxD2 pin
on the rising edge of the serial clock pulse, while
receive data is fetched from the RxD2 pin on the falling
edge of the serial clock pulse.
When data is fetched, data is transferred from the shift
registers to the buffer registers and buffer-full interrupt
INTRX2 is genrated to request receive data read.
When the interrupt service program reads the next
receive data from the buffer register, the interrupt
request signal is cleared.
(Internal clock pulses)
In the internal clock operation, a wait begins until the
received data is read and the next send data is written.
(External clock pulses)
In the external clock operation, the receive data must
be read and the next send data written before starting
the next shift operation, because the shift operation is
synchronized with the external supplied clock pulses.
operation is determined by the maximum delay time
from interrupt request generation to send data fetch
and receive data write.
Because the same buffer registers are used for send
and receive, always ensure that send data is written
after 8 bits of receive data are fetched.
To end send-receive, disable the serial transfer control
register. When the serial transfer control register is dis-
abled, send-receive ends afetr receive data is orga-
nized and transferred to the buffer register.
The program checks the end of send-receive by read-
ing serial transfer monitor flags SCMOD2 <FFSI>.
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| TMP90PH02 | A System Evaluation LSI With 8-Bit CPU,One-Time PROM(16384 x 8-Bit),RAM(512 x 8-Bit)(系統(tǒng)評(píng)估大規(guī)模集成電路（集成8位CPU，一次可編程ROM(16384 x 8位),RAM(512 x 8位)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP90CM36F | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM36T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM37F | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller |
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| TMP90CM38F | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller |
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