參數資料
型號: TMP96C031
廠商: Toshiba Corporation
英文描述: High Speed Advanced CMOS 16-bit Microcontroller For Controlling Medium to Large-Scale Equipment(用于中等到大型設備控制,高速、先進的 CMOS 16位微控制器)
中文描述: 采用先進的CMOS高速16位微控制器控制中的大型設備(用于中等到大型設備控制,高速,先進的的CMOS 16位微控制器)
文件頁數: 124/186頁
文件大?。?/td> 5299K
代理商: TMP96C031
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124
TOSHIBA CORPORATION
TMP96C031N/F
data is evaluated as “1”. The sampled data “0", “0” and
“1” is evaluated that the received data is “0”.
Receiving Control
I/O interface mode (channel 1 only)
When in SCLK1 output mode with the setting of
SC1CR <IOC> = “0", RxD1 signal will be sampled at the
rising edge of shift clock which is output to SCLK pin.
When in SCLK input mode with the setting SC1CR
<IOC> = “1", RxD1 signal will be sampled at the rising
edge or falling edge of SCLK input according to the set-
ting of SC1CR <SCLKS> register.
Asynchronous Communication (UART) mode
The receiving control has a circuit for detecting the
start bit by the rule of majority. When two or more “0” are
detected during 3 samples, it is recognized as start bit
and the receiving operation is started.
Data being received is also evaluated by the rule of
majority.
Receiving Buffer
To prevent overrun error, the receiving buffer has a
double buffer structure.
Received data is stored one bit by one bit in the
receiving buffer 1 (shift register type). When 7 bits or 8
bits of data are stored in the receiving buffer 1, the stored
data is transferred to another receiving buffer 2
(SC0BUF/SC1BUF), generating an interrupt INTRX0/
INTRX1. The CPU reads only receiving buffer 2
(SC0BUF/SC1BUF). Even before the CPU reads the
receiving buffer 2 (SC0BUF/SC1BUF), the received data
can be stored in the receiving buffer 1. However, unless
the receiving buffer 2 (SC0BUF/SC1BUF) is read before
all bits of the next data are received by the receiving
buffer 1, an overrun error occurs. If an overrun error
occurs, the contents of the receiving buffer 1 will be lost,
although the contents of the receiving buffer 2 and
SC0CR <RB8> SC1CR <RB8> are still preserved.
The parity bit added in 8-bit UART mode and the
most significant bit (MSB) in 9-bit UART mode are stored
in SC0CR <RB8>/SC1CR <RB8>.
When in 9-bit UART mode, the wake-up function of
the slave controllers is enabled by setting SC0MOD
<WU>/SC1MOD <WU> to “1", and interrupt INTRX0/
INTRX1 occurs only when SC0CR <RB8>/SC1CR
<RB8> is set to “1”.
Transmission Counter
Transmission counter is a 4-bit binary counter which
is used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK clock,
generating TxDCLK every 16 clock pulses.
Figure 3.10 (14). Generation of Transmission Clock
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相關代理商/技術參數
參數描述
TMP96C031F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller
TMP96C031N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller
TMP96C031ZF 制造商:Toshiba America Electronic Components 功能描述:MCU 16BIT TLCS-900 CISC ROMLESS 5V 64PQFP - Bulk
TMP96C041AF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller
TMP96C041AFG 制造商:Toshiba America Electronic Components 功能描述: