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參數(shù)資料
| 型號： | TMP96C141AF |
| 廠商： | Toshiba Corporation |
| 英文描述： | High Speed Advanced CMOS 16-bit Microcontroller For Controlling Medium to Large-Scale Equipment(用于中等到大型設(shè)備控制，高速、先進(jìn)的 CMOS 16位微控制器) |
| 中文描述： | 采用先進(jìn)的CMOS高速16位微控制器控制中的大型設(shè)備（用于中等到大型設(shè)備控制，高速，先進(jìn)的的CMOS 16位微控制器） |
| 文件頁數(shù)： | 16/178頁 |
| 文件大?。?/td> | 5667K |
| 代理商： | TMP96C141AF |
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16
TOSHIBA CORPORATION
TMP96C141AF
<Usage of read only mode (DRAM refresh)>
When the hardware configuration is as follows:
DRAM mapping size:
DRAM data bus size:
DRAM mapping address range:
= 1MB
= 8 bits
= 100000H to
1FFFFFH
Set the following registers first; refresh is performed
automatically.
Register initial value setting
LD
LDC
LD
LDC
XIX, 100000H
DMAS0,XIX
A, 00001010B
DMAM0,
…
mapping start address
A
DRAM refresh)
…
read only mode (for
Timer Setting
Set the timers so that interrupts are generated at
intervals of 62.5
μ
s or less.
Interrupt controller setting
Set the timer interrupt mask h other interrupt mask.
Write the above timer interrupt vector value in the
High-Speed
μ
DMA start vector register, DMA0V.
(Operation description)
The DRAM data bus is an 8-bit bus and the micro
DMA is in read-only mode (4 bytes), so refresh is per-
formed four times per interrupt.
When a 512 refresh/8ms DRAM is connected, DRAM
refresh is performed sufficiently if the micro DMA is
started every 15.625
μ
s x 4 = 62.4
timing is 15.625
μ
s/refresh.
(Overhead)
Each processing time by the micro DMA is 1.8
states) @ 20MHz with an 8-bit data bus.
In the above example, the micro DMA is started every
62.5
μ
s, 1.8
μ
s/62.5
μ
s = 0.029; thus, the overhead is
2.9%.
3.3.3 Interrupt Controller
Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The
left half of the diagram shows the interrupt controller; the right
half includes the CPU interrupt request signal circuit and the
HALT release signal circuit.
Each interrupt channel (total of 20 channels) in the inter-
rupt controller has an interrupt request flip-flop, interrupt prior-
μ
s or less, since the
μ
s (18
ity setting register, and a register for storing the high-speed
micro DMA start vector. The interrupt request flip-flop is used
to latch interrupt requests from peripheral devices. The flip-flop
is cleared to 0 at reset, when the CPU reads the interrupt
channel vector after the acceptance of interrupt, or when the
CPU executes an instruction that clears the interrupt of that
channel (writes 0 in the clear bit of the interrupt priority setting
register).
For example, to clear the INT0 interrupt request, set the
register after the
as follows.
DI instruction
INTE0AD
←
---- 0 ---
Zero-clears the INT0 Flip-Flop.
The status of the interrupt request flip-flop is detected by
reading the clear bit. Detects whether there is an interrupt
request for an interrupt channel.
The interrupt priority can be set by writing the priority in
the interrupt priority setting register (e.g., INTE0AD, INTE45,
etc.) provided for each interrupt source. Interrupt levels to be
set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis-
ables the corresponding interrupt request. The priority of the
non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed
to 7. If interrupt requests with the same interrupt level are gen-
erated simultaneously, interrupts are accepted in accordance
with the default priority (the smaller the vector value, the higher
the priority).
The interrupt controller sends the interrupt request with
the highest priority among the simultaneous interrupts and its
vector address to the CPU. The CPU compares the priority
value <IFF2 to 0> set in the Status Register by the interrupt
request signal with the priority value sent; if the latter is higher,
the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1 in the CPU SR<IFF2 to 0>. Interrupt
requests where the priority value equals or is higher than the
set value are accepted simultaneously during the previous
interrupt routine. When interrupt processing is completed (after
execution of the RETI instruction), the CPU restores the priority
value saved in the stack before the interrupt was generated to
the CPU SR<IFF2 to 0>.
The interrupt controller also has four registers used to
store the high-speed micro other DMA start vector. These are I/
O registers; unlike other DMA registers (DMAS, DMAD, DMAM,
and DMAC), they can be accessed in either normal or system
mode. Writing the start vector of the interrupt source for the
micro DMA processing (see Table 3.3 (1)), enables the corre-
sponding interrupt to be processed by micro DMA processing.
The values must be set in the micro DMA parameter registers
(e.g., DMAS and DMAD) prior to the micro DMA processing.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP96C141BF | 功能描述:16位微控制器 - MCU ROMLESS TLCS 900 w/ 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| TMP96C141BFG | 功能描述:16位微控制器 - MCU 900 Romless MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| TMP96CM40F | 制造商:Toshiba America Electronic Components 功能描述:TLCS900 M/ROM, 32K ROM , 1K RAM - Tape and Reel |
| TMP96PM40F | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Quality And Reliability Assurance / Handling Precautions |
| TMP96PM40F(Z) | 功能描述:16位微控制器 - MCU 32K ROM OTP 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
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