參數(shù)資料
型號: TMP96C141AF
廠商: Toshiba Corporation
英文描述: High Speed Advanced CMOS 16-bit Microcontroller For Controlling Medium to Large-Scale Equipment(用于中等到大型設備控制,高速、先進的 CMOS 16位微控制器)
中文描述: 采用先進的CMOS高速16位微控制器控制中的大型設備(用于中等到大型設備控制,高速,先進的的CMOS 16位微控制器)
文件頁數(shù): 94/178頁
文件大?。?/td> 5667K
代理商: TMP96C141AF
94
TOSHIBA CORPORATION
TMP96C141AF
Up-counter (UC4/UC5)
UC4/UC5 is a 16-bit binary counter which counts up
according to the input clock specified by T4MOD
<T4CLK1, 0> or T5MOD <T5CLK1, 0> register.
As the input clock, one of the internal clocks
φ
T1 (8/
fc),
φ
T4 (32/fc), and
φ
T16 (128/fc) from 9-bit prescaler
(also used for 8-bit timer), and external clock from TI4 pin
(also used as P80/INT4 pin) or TI6 (also used as P84/
INT6 pin) can be selected. When reset, it will be initialized
to <T4CLK1, 0>/<T5CLK1, 0> = 00 to select TI4/TI6
input mode. Counting or stop and clear of the counter is
controlled by timer operation control register TRUN
<T4RUN, T5RUN>.
When clearing is enabled, up-counter UC4/UC5 will
be cleared to zero each time it coincides matches the
TREG4
TREG5
Upper 8 bits
000031H
Lower 8 bits
000030H
Upper 8 bits
000033H
Lower 8 bits
000032H
TREG6
TREG7
Upper 8 bits
000041H
Lower 8 bits
000040H
Upper 8 bits
000043H
Lower 8 bits
000042H
timer register TREG5, TREG7. The “clear enable/disable”
is set by T4MOD <CLE> and T5MOD <CLE>.
If clearing is disabled, the counter operates as a free-
running counter.
Timer Registers
These two 16-bit registers are used to set the interval
time. When the value of up-counter UC4/UC5 matches
the set value of this timer register, the comparator match
detect signal will be active.
Setting data for timer register (TREG4, TREG5,
TREG6 and TREG7) is executed using 2 byte date trans-
fer instruction or using 1 byte date transfer instruction
twice for lower 8 bits and upper 1 bits in order.
TREG4 and TREG6 timer register is of double buffer
structure, which is paired with register buffer. The timer
control register T45CR <DB4EN, DB6EN> controls
whether the double buffer structure should be enabled or
disabled. : disabled when <DB4EN, DB6EN> = 0, while
enabled when <DB4EN, DB6EN> = 1.
When the double buffer is enabled, the timing to
transfer data from the register buffer to the timer register
is at the match between the up-counter (UC4/UC5) and
timer register TREG5/TREG7.
When reset, it will be initialized to <DB4EN, DB6EN>
= 0, whereby the double buffer is disabled. To use the
double buffer, write data in the timer register, set
<DB4EN, DB6EN> = 1, and then write the following data
in the register buffer.
TREG4, TREG6 and register buffer are allocated to
the same memory addresses 000030H/000031H/
0000400H/000041H. When <DB4EN, DB6EN> = 0,
same value will be written in both the timer register and
register buffer. When <DB4EN, DB6EN> = 1, the value is
written into only the register buffer.
Capture Register
These 16-bit registers are used to hold the values of
the up-counter.
Data in the capture registers should be read by a 2-
byte data load instruction or two 1-byte data load instruc-
tion, from the lower 8 bits followed by the upper 8 bits.
Capture Input Control
This circuit controls the timing to latch the value of
up-counter UC4/UC5 into (CAP1, CAP2)/(CAP3, CAP4).
CAP 1
CAP 2
Upper 8 bits
000035H
Lower 8 bits
000034H
Upper 8 bits
000037H
Lower 8 bits
000036H
CAP 3
CAP 4
Upper 8 bits
000045H
Lower 8 bits
000044H
Upper 8 bits
000047H
Lower 8 bits
000046H
The latch timing of capture register is controlled by regis-
ter T4MOD <CAP12M1, 0>/T5MOD <CAP34M1, 0>.
When T4MOD <CAP12M1, 0>/T5MOD
<CAP34M1, 0> = 00
Capture function is disabled. Disable is the
default on reset.
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TMP96PM40F(Z) 功能描述:16位微控制器 - MCU 32K ROM OTP 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT