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參數(shù)資料
| 型號： | TMPR3904AF |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32 Bit TX39 Family System RISC Microprocessor(32位TX39系列簡化指令系統(tǒng)計算機微處理器) |
| 中文描述： | 32位TX39家庭系統(tǒng)RISC微處理器（32位TX39系列簡化指令系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 209K |
| 代理商： | TMPR3904AF |
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INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
EJC-TMPR3904AF-6
14-Dec-1998
TOSHIBA CORPORATION
4.2 PIN FUNCTIONS
Name
System Interface
SYSCLK
I/O
5V tolerant
input
Function
O
-
System Clock
Outputs a clock with frequency either equal to or half of that
of the TX39 Processor Core.
Address bus. It is an output when the TX3904A is a bus
master, an input in otherwise.
A[31:24] are shared with PIO2.
Byte Enable
Indicates valid data positions on the data bus D[31:0]. It is an
output when the TX3904A is a bus master, an input in
otherwise.
BE[3]* : D[31:24]
BE[2]* : D[23:16]
BE[1]* : D[15:8]
BE[0]* : D[7:0]
Data bus.
D[15:0] is used in 16-bit bus mode.
System Chip Select
Asserts when accessing the address range that is set by the
internal register.
Read/Write
Indicates the bus operation being executed is either read or
write. It is an output when the TX3904A is a bus master, an
input in otherwise.
High: Read
Low: Write
Bus Start
Asserts during the first clock period of the bus operation. It is
an output when the TX3904A is a bus master, an input in
otherwise.
Last
Indicates that it is the last of the bus operation. It is an output
when the TX3904A is a bus master, an input in otherwise.
Acknowledge
Slave devices inform the bus master that the bus operation
may be finished. It is an input when the TX3904A is a bus
master, an output in otherwise.
A[31:1]
(PIO2[7:0])
I/O A
I/O A
BE[3:0]*
I/O A
D[31:0]
I/O A
SCS[3:0]*
O
-
R/W*
I/O A
BSTART*
I/O A
LAST*
I/O A
ACK*
I/O A
5V tolerant input : A = Available, N.A = Not Available
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