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參數(shù)資料
| 型號(hào)： | TMS27C256-150 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Programmable Read-Only Memory(32K×8結(jié)構(gòu),可擦可編程只讀存儲(chǔ)器) |
| 中文描述： | 可編程只讀存儲(chǔ)器（32K的× 8結(jié)構(gòu)，可擦可編程只讀存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | TMS27C256-150 |
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TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS256G – SEPTEMBER 1984 – REVISED JUNE 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level except for V
PP
during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature
mode.
FUNCTION
MODE
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
VIL
VIL
VCC
VCC
X
VIL
VIH
VCC
VCC
X
VIH
X
VIL
VIH
VPP
VCC
X
VIH
VIL
VPP
VCC
X
VIH
X
VIL
VIL
VCC
VCC
G
VPP
VCC
A9
VCC
VCC
X
VPP
VCC
X
VH
VIL
VH
VIH
A0
X
X
X
X
X
X
DQ0 DQ7
DQ0–DQ7
Data Out
Hi Z
Hi-Z
Hi Z
Hi-Z
Data In
Data Out
Hi Z
Hi-Z
CODE
MFG
DEVICE
97
04
X can be VIL or VIH.
VH = 12 V
±
0.5 V.
read/output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
CC
supply current can be reduced from 30 mA to 500
μ
A (TTL-level inputs) or 250
μ
A (CMOS-level
inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure (TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 ). EPROM erasure before programming is necessary to
assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
intensity
×
exposure time) is 15-W
s/cm
2
. A typical 12-mW/cm
2
, filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS27C256-150JL | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:EPROM, 32K x 8, 28 Pin, Ceramic, DIP |
| TMS27C256-15JE4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| TMS27C25615JL | 制造商:TI 功能描述:New 制造商:Texas Instruments 功能描述: |
| TMS27C256-15JL | 制造商:Texas Instruments 功能描述:EPROM, 32K x 8, 28 Pin, Ceramic, DIP |
| TMS27C256-15JL4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
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