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參數(shù)資料
| 型號： | TMS27C256-150 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Programmable Read-Only Memory(32K×8結構,可擦可編程只讀存儲器) |
| 中文描述： | 可編程只讀存儲器（32K的× 8結構，可擦可編程只讀存儲器） |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 280K |
| 代理商： | TMS27C256-150 |
TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE
TMS27PC256 262144-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS256G – SEPTEMBER 1984 – REVISED JUNE 1995
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics over recommended range of operating conditions
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C256-10
’27PC256-10
’27C256-12
’27PC256-12
’27C256-15
’27PC256-15
UNIT
MIN
MAX
100
MIN
MAX
120
MIN
MAX
150
ta(A)
ta(E)
ten(G)
Access time from address
CL = 100 pF,
1 Series 74 TTL Load,
Input tr
≤
20 ns,
Input tf
≤
20 ns
100 F
100 F
ns
Access time from chip enable
100
120
150
ns
Output enable time from G
55
55
75
ns
tdis
Output disable time from G or E, whichever
occurs first
0
45
0
45
0
60
ns
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first
0
0
0
ns
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C256-17
’27PC256-17
’27C256-20
’27PC256-20
’27C256-25
’27PC256-25
UNIT
MIN
MAX
170
MIN
MAX
200
MIN
MAX
250
ta(A)
ta(E)
ten(G)
Access time from address
CL = 100 pF,
1 Series 74 TTL Load,
Input tr
≤
20 ns,
Input tf
≤
20 ns
100 F
100 F
ns
Access time from chip enable
170
200
250
ns
Output enable time from G
75
75
100
ns
tdis
Output disable time from G or E, whichever
occurs first
0
60
0
60
0
60
ns
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first
Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
0
0
0
ns
switching characteristics for programming: V
CC
= 6.50 V and V
PP
= 13 V (SNAP! Pulse), T
A
= 25
°
C
(see Note 3)
PARAMETER
MIN
MAX
130
UNIT
ns
tdis(G)
ten(G)
NOTES:
Output disable time from G
0
Output enable time from G
150
ns
3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low). (Reference page 9.)
4. Common test conditions apply for the tdis except during programming.
recommended timing requirements for programming: V
CC
= 6.5 V and V
PP
= 13 V,
T
A
= 25
°
C (see Note 3)
MIN
NOM
MAX
UNIT
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
th(A)
th(D)
tw(IPGM)
tsu(A)
tsu(G)
tsu(E)
tsu(D)
tsu(VPP)
tsu(VCC)
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low). (Reference page 9.)
Hold time, address
0
Hold time, data
2
Pulse duration, initial program
95
100
105
Setup time, address
2
Setup time, G
2
Setup time, E
2
Setup time, data
2
Setup time, VPP
Setup time, VCC
2
2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS27C256-150JL | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:EPROM, 32K x 8, 28 Pin, Ceramic, DIP |
| TMS27C256-15JE4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
| TMS27C25615JL | 制造商:TI 功能描述:New 制造商:Texas Instruments 功能描述: |
| TMS27C256-15JL | 制造商:Texas Instruments 功能描述:EPROM, 32K x 8, 28 Pin, Ceramic, DIP |
| TMS27C256-15JL4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EPROM |
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